E.G.T. Jaspers, Peter H. N. de With,
... bit wide memory bus. For double-data-rate SDRAM (DDR SDRAM), the proposed mapping strategy reduces the bandwidth in ...
Tópico(s): Video Coding and Compression Technologies
2001 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Consumer Electronics
David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, K. Baynes, Aamer Jaleel, Bruce Jacob,
... models for a variety of existing memories, including SDRAM, DDR, DDR2, DRDRAM and FB-DIMM, with the capability to easily vary their parameters. It also models the power consumption of SDRAM and its derivatives. It can be used as ...
Tópico(s): Low-power high-performance VLSI design
2005 - ACM SIGARCH | ACM SIGARCH Computer Architecture News
S. Kuge, T. Kato, K. Furutani, S. Kikuda, K. Mitsui, T. Hamamoto, J. Setogawa, K. Hamade, Yuichiro Komiya, S. Kawasaki, T. Kono, T. Amano, Takahiro Kubo, Manabu Haraguchi, Y. Nakaoka, Masatoshi Akiyama, Y. Konishi, H. Ozaki, T. Yoshihara,
A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation.
Tópico(s): VLSI and Analog Circuit Testing
2000 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
Young-Jin Jeon, Joong-Ho Lee, Hyun‐Chul Lee, Kyo-Won Jin, Kyeong‐Sik Min, Jinyong Chung, H.-J. Park,
... 266 Mb/s in the production 256-Mb DDR SDRAM. The worst-case power consumption and the chip ...
Tópico(s): Radio Frequency Integrated Circuit Design
2004 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
Chulwoo Kim, Hyun-Woo Lee, Junyoung Song,
... SDR) synchronous DRAM (SDRAM)to double-data-rate (DDR) SDRAM. Recently developed versions of low-power DDR four (LPDDR4) and synchronous graphics DDR five (GDDR5) ...
Tópico(s): Parallel Computing and Optimization Techniques
2016 - Institute of Electrical and Electronics Engineers | IEEE Solid-State Circuits Magazine
Richard Tansey, Mark Neal, Ray Carroll,
... because Infineon used an ordinary bus in its SDRAM and DDR DRAM memory devices. He ruled that the term " ...
Tópico(s): Corporate Insolvency and Governance
2005 - Taylor & Francis | Industry and Innovation
T. Hamamoto, K. Furutani, Tetsuo Kubo, S. Kawasaki, H. Iga, T. Kono, Y. Konishi, T. Yoshihara,
... over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica ...
Tópico(s): Low-power high-performance VLSI design
2004 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
T. Kirihata, Georg Mueller, Bing Ji, G. Frankowsky, Joe Ross, H. Terletzki, D.G. Netis, O. Weinfurtner, David R. Hanson, D Gomon, L. Hsu, D.W. Sotraska, A.M. Reith, M.A. Hug, K.P. Guay, M. Selz, P. Poechmueller, H. Hoenigschmid, M.R. Wordeman,
... 2/, 16-bank, 1-Gb, double-data-rate (DDR) synchronous dynamic random access memory (SDRAM) has been fabricated in fully planarized 0.175-/ ...
Tópico(s): Cellular Automata and Applications
1999 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
Jérémie Crenne, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan,
... double data rate synchronous dynamic random access memory (DDR-SDRAM) via a microprocessor. Following application loading, the core- ...
Tópico(s): Advanced Malware Detection Techniques
2013 - Association for Computing Machinery | ACM Transactions on Embedded Computing Systems
Daniel Llamocca, Marios S. Pattichis,
... and their PPA/EPA values are stored in DDR-SDRAM and can be chosen dynamically to meet time- ...
Tópico(s): Advanced Memory and Neural Computing
2012 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Circuits and Systems for Video Technology
Iwata Ken-ichi, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori,
... stream from a 64 b width low-power DDR-SDRAM at an operating frequency of 166 MHz at ...
Tópico(s): Digital Filter Design and Implementation
2010 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
Thomas Häuser, Aravind Dasu, Arvind Sudarsanam, S. Young,
... levels of a hierarchical memory system (hard disk, DDR SDRAMs and FPGA block RAMS) using completely pipelined data ...
Tópico(s): Algorithms and Data Compression
2007 - | Scalable Computing Practice and Experience
Peter C. Dillinger, J.F. Vogelbruch, Jessica Leinen, Sergey Suslov, R. Patzak, Hanspeter Winkler, Karsten Schwan,
... date Virtex-II Pro architecture, two large independent DDR-SDRAM channels, two fast independent ZBT-SRAM channels, and ...
Tópico(s): CCD and CMOS Imaging Sensors
2006 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Nuclear Science
M. Wazlowski, N. R. Adiga, D.K. Beece, R. Bellofatto, Matthias A. Blumrich, D. Chen, M.B. Dombrowa, Alan Gara, Mark Giampapa, R.A. Haring, P. Heidelberger, D. Hoenicke, B.J. Nathanson, Martin Ohmacht, R. Sharrar, S. N. Singh, Burkhard Steinmacher-Burow, R. B. Tremaine, M. Tsao, A. R. Umamaheshwaran, Pavlos Vranas,
... double-data-rate synchronous dynamic random access memory (DDR SDRAM) memory controller, a collective network interface, a torus ...
Tópico(s): Radiation Effects in Electronics
2005 - IBM | IBM Journal of Research and Development
... communication (Responsive Link II), computer I/O peripherals (DDR SDRAM I/Fs, DMAC, PCI-X, USB2.0, IEEE1394, ...
Tópico(s): Parallel Computing and Optimization Techniques
2005 - Fuji Technology Press Ltd. | Journal of Robotics and Mechatronics
Sang-Bo Lee, Seong-Jin Jang, Jin-Seok Kwak, Sang-Jun Hwang, Seong‐Ho Cho, Min Sang Park, Ho-Kyoung Lee, Woojin Lee, Yu-Rim Lee, Young-Cheol Cho, Hyoung-Jo Heo, Won-Hwa Shin, Jong‐Soo Lee, Yun-Sik Park, Seok Jung Kim, Young-Uk Jang, Seok-Won Hwang, Young-Hyun Jun, Soo-In Cho,
An 8 M /spl times/ 32 GDDR (graphic DDR) SDRAM operating up to 800-MHz clock (CLK) frequency ...
Tópico(s): Low-power high-performance VLSI design
2005 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
Changsik Yoo, Kye-Hyun Kyung, Kyu-Nam Lim, Hi-Choon Lee, J.-W. Chai, Nak-Won Heo, Dong‐Jin Lee, Chang‐Hyun Kim,
A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-/spl mu/m ...
Tópico(s): Advancements in PLL and VCO Technologies
2004 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
... real-time communication, and I/O peripherals including DDR SDRAM I/Fs, DMAC, PCI64, USB2.0, IEEE1394, PWM ...
Tópico(s): Real-Time Systems Scheduling
2004 - Fuji Technology Press Ltd. | Journal of Robotics and Mechatronics
Kuen‐Phon Wu, Chih-Wei Wu, Ya-Ping Tsao, Ting-Wei Kuo, Yuan‐Chao Lou, Cheng‐Wen Lin, Suh‐Chin Wu, Jya‐Wei Cheng,
... 4 1.8 GHz CPU and 512 MB DDR-SDRAM. The structures were calculated and refined with ab ...
Tópico(s): Insect symbiosis and bacterial influences
2003 - Elsevier BV | Journal of Biological Chemistry
Gregg E. Favalora, Rick K. Dorval, Deirdre M. Hall, Michael Giovinco, Joshua Napoli,
... image slices, as well as 6 Gbits of DDR SDRAM graphics memory.
Tópico(s): Augmented Reality Applications
2001 - SPIE | Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
C. H. Liu, Sue J. Lin, Charles Lewis,
... double data rate synchronous dynamic random access memory (DDR SDRAM). The comparisons between these two impact methods and ...
Tópico(s): Recycling and Waste Management Techniques
2009 - Elsevier BV | Journal of Cleaner Production
... to eliminate external memory bottlenecks, a bandwidth- optimized DDR-SDRAM memory controller has been designed for use with ...
Tópico(s): Parallel Computing and Optimization Techniques
2008 - Institute of Electrical and Electronics Engineers | Proceedings - IEEE International Parallel and Distributed Processing Symposium
Abstract. The ever increasing demand for bandwidth of computer-systems lead to several standards of SDRAMs. This article compares SDR, DDRI, DDRII, and RDRAM systems. Besides the overall basic innovations, differences will be discussed. Topics like architecture, interfaces, and modules are described.
Tópico(s): Advanced Data Storage Technologies
2003 - Copernicus Publications | Advances in radio science
M. Ben Olson, Brandon Kammerdiener, Michael R. Jantz, Kshitij Doshi, Terry Jones,
... present distinct advantages and tradeoffs compared to conventional DDR* SDRAM, such as higher bandwidth with lower capacity or ...
Tópico(s): Cloud Computing and Resource Management
2022 - Association for Computing Machinery | ACM Transactions on Architecture and Code Optimization
Zhujia Chen, Haigang Yang, Fei Liu, Yu Wang,
... delay-locked loop (ADDLL) is proposed for the DDR SDRAM controller interface in a field programmable gate array ( ...
Tópico(s): Radio Frequency Integrated Circuit Design
2011 - IOP Publishing | Journal of Semiconductors
... rates of the computer memory products developer's SDRAM and DDR SDRAM technologies, also ordering Rambus to desist from lying ...
Tópico(s): Advanced Data Storage Technologies
2007 - Oxford University Press | Journal of Intellectual Property Law & Practice
T. Hamamoto, M. Tsukude, Kazutami Arimoto, Y. Konishi, T. Miyamoto, H. Ozaki, Masahiro Yamada,
... a key factor in future main memory systems. DDR SDRAM (double-data-rate synchronous-DRAM) is one of ... access time and high data transfer rate for DDR-SDRAM's. First, a self-skew compensating technique enables ... random column operation. A 16-bank 256-Mbit DDR SDRAM circuit has been designed, and the possibility of the realization of random column 200 MHz/spl times/32 DDR operation, namely, 1.6-Gbyte/s data rate ...
Tópico(s): Parallel Computing and Optimization Techniques
1998 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
R. Harboe-Sørensen, F.-X. Guerre, George K. Lewis,
... ion single event effects (SEEs) in advanced commercial DDR-II SDRAM memories, a large number of practical problems need ...
Tópico(s): Advanced Memory and Neural Computing
2007 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Nuclear Science
Konstantin Bick, Duy Thanh Nguyen, Hyuk‐Jae Lee, Hyun Kim,
... integration of DRAMSim2, a simulator that thoroughly models DDR-SDRAM main memory architecture, into the application-level+ simulator ...
Tópico(s): Real-Time Systems Scheduling
2018 - Multidisciplinary Digital Publishing Institute | Electronics
Jong-Pil Son, Jin Ho Kim, Woo Song Ahn, Seung Uk Han, Byung-Sick Moon, Churoo Park, Hongsun Hwang, Seong-Jin Jang, Joo Sun Choi, Young-Hyun Jun, Soo-Won Kim,
... consumed by the internal pump circuitry. A 1Gbit DDR SDRAM is fabricated using Samsung's advanced 50nm DRAM ...
Tópico(s): Advancements in Semiconductor Devices and Circuit Design
2010 - Institute of Electrical and Electronics Engineers | Proceedings of ESSCIRC