Richard Rizzolo, T.G. Foote, J. M. Crafts, D. A. Grosch, T. O. Leung, D. J. Lund, Bruce Mechtly, Bryan Robbins, T. J. Slegel, Miguel Tremblay, Glen Wiedemeier,
... the first zSeries® product to use electronic fuses (eFUSEs). The blowing of the fuse does not involve ... the application of a higher-than-nominal voltage. eFUSEs provide several compelling advantages over the laser fuses ... process does not risk damage to adjacent devices. eFUSEs can be blown by a logic process instead of a physical laser ablation method. eFUSEs are substantially smaller than laser fuses, and they ... specialized equipment or separate product flow is required, eFUSEs can be blown at multiple test and application ...
Tópico(s): Manufacturing Process and Optimization
2007 - IBM | IBM Journal of Research and Development
Summary form only given. Programmable eFuse designs present an integration challenge in modern CMOS processing. The power level to program a fuse, and the programming methodologies leverage ... in a design avoid. A high degree of eFuse process control and circuit design is required in order to guarantee operation. Almost all eFuse types are time programmable and are limited to one chance programmable. This tutorial discussed selected eFuse technologies describing the design philosophy electrical programming and ...
Tópico(s): Low-power high-performance VLSI design
2008 - Institute of Electrical and Electronics Engineers | IEEE International Integrated Reliability Workshop final report
Jeong-Ho Kim, Du-Hwi Kim, Liyan Jin, Pan-Bong Ha, Young‐Hee Kim,
... based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to ... out of consideration for resistance variations of programmed eFuse. Peak current through the nonprogrammed eFuse is reduced from 728 ㎂ to 61 ㎂ when a ... sensing is possible even if sensed resistance of eFuse has fallen by about 9 ㏀ in a wafer ...
Tópico(s): VLSI and Analog Circuit Testing
2011 - Institute of Electronics Engineers of Korea | JSTS Journal of Semiconductor Technology and Science
C. Kothandaraman, S.K. Iyer, Shankar S. Iyer,
... of electromigration, as an electrically programmable fuse device (eFUSE). Upon programming, eFUSE's show a large increase in resistance that ... sensing. The transient device characteristics show that the eFUSE stays in a low resistance state during programming ...
Tópico(s): Molecular Junctions and Nanostructures
2002 - Institute of Electrical and Electronics Engineers | IEEE Electron Device Letters
Summary form only given. Programmable eFuse designs present an integration challenge in modern CMOS processing. The power level to program a fuse, and the programming methodologies leverage ... in a design avoid. A high degree of eFuse process control and circuit design is required in order to guarantee operation. Almost all eFuse types are one time programmable and are limited to "one chance" programmable. This tutorial discussed selected eFuse technologies describing the design philosophy electrical programming and ...
Tópico(s): Semiconductor materials and devices
2008 - Institute of Electrical and Electronics Engineers | IEEE International Integrated Reliability Workshop final report
Huiling Yang, In-Wha Choi, Ji-Hye Jang, Liyan Jin, Pan-Bong Ha, Young‐Hee Kim,
... 기반으로 PMIC용 고신뢰성 24비트 듀얼 포트(dual port) eFuse OTP 메모리를 설계하였다. 제안된 dynamic pseudo NMOS 로직회로를 ... 결과를 출력한다. 그래서 한 개의 PFb 핀만 테스트하므로 eFuse OTP 메모리가 정상적으로 프로그램 되었는지를 확인할 수 있다. 그리고 program-verify-read 모드를 이용하여 프로그램된 eFuse 저항의 변동을 고려한 가변 풀-업 부하(variable ... 35{\mu}m$ BCD 공정을 이용하여 설계된 24비트 eFuse OTP 메모리의 레이아웃 면적은 $289.9{\mu}m{\ ... process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose ... out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a ...
Tópico(s): Semiconductor materials and devices
2012 - | The Journal of the Korean Institute of Information and Communication Engineering
Du-Hwi Kim, Ji-Hye Jang, Liyan Jin, Jae‐Hyung Lee, Pan-Bong Ha, Young‐Hee Kim,
We propose a low-power eFuse one-time programmable (OTP) memory IP based on a bipolar CMOS DMOS (BCD) process. It is an eFuse OTP memory cell which uses separate transistors that ... optimized in program and in read mode. The eFuse cell also uses poly-silicon gates having co- ... used for the low-power and small-area eFuse OTP memory IP. Additionally, we propose a new ... silicon and p+ poly-silicon to optimize the eFuse link. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0. ...
Tópico(s): Low-power high-performance VLSI design
2010 - Institute of Electronics, Information and Communication Engineers | IEICE Transactions on Electronics
Sami Rosenblatt, Srivatsan Chellappa, Albert Cestero, Norman Robson, T. Kirihata, Subramanian S. Iyer,
... authenticating chips uses 4 Kb electrically programmable fuses (eFUSE) to store bit strings representing encrypted intrinsic fingerprints ... then compared with the bit strings in the eFUSE. Monte Carlo simulations demonstrate that, targeting an average ...
Tópico(s): Advanced Memory and Neural Computing
2013 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
Anil Indluru, E. Misra, T. L. Alford,
... a potential application as an electrically programmable fuse (eFUSE) device by local Joule heating induced at high ... failure sites, the dominant failure mechanism in Ag eFUSEs with TiN barrier layer under these current densities ... determining the failure time in these types of eFUSEs.
Tópico(s): Integrated Circuits and Semiconductor Failure Analysis
2009 - Institute of Electrical and Electronics Engineers | IEEE Electron Device Letters
Wooyoung Jeong, Wen-Chao Hao, Pan-Bong Ha, Young‐Hee Kim,
본 논문에서는 eFuse OTP 메모리가 넓은 동작전압 영역을 갖도록 하기 위해서 V2V(=2V±10％)의 regulation된 전압을 이용한 RWL 구동회로와 BL ... 경우에 대해 OTP IP 크기를 비교한 결과 32비트 eFuse OTP의 레이아웃 면적은 각각 735.96㎛ × 61.605㎛ (= ... 525㎛ (=0.01768㎜ 2 )로 4행 × 8열의 32비트 eFuse OTP 사이즈가 1행 × 32열의 32비트 eFuse OTP 사이즈보다 더 작은 것을 확인하였다.
Tópico(s): Low-power high-performance VLSI design
2014 - | The Journal of the Korean Institute of Information and Communication Engineering
Gary M. Vilke, Winfred Sardar, Roger Fisher, James D. Dunford, Theodore C. Chan,
To obtain medical follow-up and determine reasons why elderly patients access paramedics via 9-1-1 and then refuse transport.A telephone survey of patients aged 65 years and older who refused transport and signed out against medical advice (AMA) after accessing paramedics via 9-1-1 was performed to obtain information about the patients' experiences, reasons why they refused, medical follow-up, and patient outcomes.One hundred of 121 (83%) patients who were contacted by telephone participated in the ...
Tópico(s): Emergency and Acute Care Studies
2002 - Taylor & Francis | Prehospital Emergency Care
C. Tian, B. Park, C. Kothandaraman, John Safran, D. Kim, Norman Robson, S.K. Iyer,
... reliability of CoSi2/p-poly Si electrical fuse (eFUSE) programmed by electromigration for 90nm technology will be ...
Tópico(s): Semiconductor materials and interfaces
2006 - Institute of Electrical and Electronics Engineers | IEEE International Reliability Physics Symposium proceedings
Ji-Hye Jang, Liyan Jin, Hwang-Gon Jeon, Kwang-Il Kim, Pan-Bong Ha, Young‐Hee Kim,
Tópico(s): Advanced Memory and Neural Computing
2012 - Springer Science+Business Media | Journal of Central South University
Tomoyuki Arai, Tatsunori Usugi, Tomotoshi Murakami, Shuya Kishimoto, Yoshiyuki Utagawa, Masato Kohtani, Ikuma Ando, Kazuhiro Matsunaga, Chihiro Arai, S. Yamaura,
... in-self-test (BIST) circuits, an SRAM, an eFuse, a temperature compensation calibration loop with a lookup ...
Tópico(s): Electromagnetic Compatibility and Measurements
2021 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
Jung Ho Kim, Ji-Hye Jang, Liyan Jin, Pan-Bong Ha, Young‐Hee Kim,
본 논문에서는 대기 상태에서 저전력 eFuse OTP 메모리 IP를 구현하기 위해 속도가 문제가 되지 않는 반복되는 블록 회로에서 1.2Ⅴ로직 트랜지스터 대신 누설 (off-leakage) 전류가작은 3. ... 줄여 동작전류 소모를 줄이는 듀얼 포트 (Dual-Port) eFuse 셀을 사용하였다. 프로그램 전압에 대한 eFuse에 인가되는 프로그램 ... 90나노 CMOS 이미지 센서 공정을 이용하여 설계된 512비트 eFuse OTP 메모리 IP의 레이아웃 크기는342㎛× 236㎛이며, 5Ⅴ의 ...
Tópico(s): CCD and CMOS Imaging Sensors
2010 - | The Journal of the Korean Institute of Information and Communication Engineering
... semiconductor circuits. According to IBM, combining the new eFuse technology with already available on-chip built-in ...
Tópico(s): Integrated Circuits and Semiconductor Failure Analysis
2004 - Institute of Electrical and Electronics Engineers | IEEE Spectrum
Mattia Balutto, Giacomo Ripamonti, Pablo Antoszczuk, Stefano Michelis, Federico Iob, Alessandro Dago, Stefano Saggini,
... buck converter, a hot-swap controller, or an eFuse is employed. Additionally, achieving the zero-current switching ...
Tópico(s): Wireless Power Transfer Systems
2023 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Power Electronics
Mathieu Gross, Nisha Jacob, Andreas Zankl, Georg Sigl,
... via the manipulation of Battery-Backed RAM and eFuses from malicious logic.
Tópico(s): Advanced Malware Detection Techniques
2021 - Springer Science+Business Media | Journal of Cryptographic Engineering
Honggyun Kim, Jamal Aziz, Vijay D. Chavan, Deok-kee Kim,
Conventional electrically programmable fuse (eFuse) includes a cathode, anode and a fuse link in between, which can be programmed by an external stimulus. In this study, programming characteristics of M1 and M2 Cu eFuse with or without a programming transistor were investigated in 28-nm CMOS technology. M2 eFuse showed a lower programming current density than M1 eFuse, and wide eFuse (M1or M2) showed a lower programming current density than narrow eFuse. Also, the heat dissipation in M2 eFuse was ...
Tópico(s): Advanced Memory and Neural Computing
2023 - Elsevier BV | Current Applied Physics
Jae‐Hyung Lee, Hwang-Gon Jeon, Kwang-Il Kim, Ki-Jong Kim, Yining Yu, Pan-Bong Ha, Young‐Hee Kim,
... 낮아지더라도 외부 프로그램 전원을 사용하여 높은 프로그램 파워를 eFuse (electrical fuse)에 공급하면서 셀의 읽기 전류를 줄일 수 있는 듀얼 포트 eFuse 셀을 제안하였다. 그리고 제안된 듀얼 포트 eFuse 셀은 파워-온 읽기 기능으로 eFuse의 프로그램 정보가 ... electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the ... supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum ...
Tópico(s): Semiconductor materials and devices
2010 - | The Journal of the Korean Institute of Information and Communication Engineering
Jae‐Hyung Lee, Min-Cheol Kang, Liyan Jin, Ji-Hye Jang, Pan-Bong Ha, Young‐Hee Kim,
We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at ... used for a low-power and small-area eFuse OTP memory IP. It is shown by a ... 3A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0. ...
Tópico(s): Advanced Memory and Neural Computing
2009 - | The Journal of the Korean Institute of Information and Communication Engineering
Melissa van der Windt, Sam Schoenmakers, Sten P. Willemsen, Lenie van Rossem, Régine P.M. Steegers‐Theunissen,
... Methods The eHealth and Face-to-face Counseling (eFUSE) study follows a single-center two-arm randomized ...
Tópico(s): Gestational Diabetes Research and Management
2021 - JMIR Publications | JMIR Research Protocols
Chang-Chien Wong, Sheng-Po Chang, Ching-Hsiang Tseng, Wei-Shou Chen, Shoou‐Jinn Chang,
The fabrication of an active electrically programmable fuse (eFuse) on a silicon-on-insulator (SOI) substrate fully ... inherently provides an isolation environment for an active eFuse. N- and P-type active fuses are programmed ...
Tópico(s): Ferroelectric and Negative Capacitance Devices
2018 - Institute of Physics | ECS Journal of Solid State Science and Technology
Yoon-kyu Kim, Ji-Hye Jang, Geon-soo Yoon, Dong-Hoon Lee, Man-yeong Ha, Pan-Bong Ha, Young‐Hee Kim,
Tópico(s): Parallel Computing and Optimization Techniques
2012 - Springer Science+Business Media | Journal of Central South University
Michael Gerten, Stephan Frei, Michael Kiffmeier, Oliver Bettgens,
In future automotive power supply systems, electronic fuses (eFuses) will be increasingly used for wire protection and controlling the power flow. However, the impact of eFuses on the overall power supply system is not ... On the one hand, it is shown, that eFuses generate less critical overvoltages compared to melting fuses. ... other hand, the high current pulses caused by eFuse switching can trigger other eFuses in other remote branches to trip. With melting ...
Tópico(s): Lightning and Electromagnetic Phenomena
2023 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Transportation Electrification
Ji-Suk Kim, Earl Kim, Daehyeon Lee, Taeheon Lee, Daesik Ham, Miju Yang, Wanha Hwang, Jaeyoung Kim, Sang-Yong Yoon, Youngwook Jeong, Eun-Kyoung Kim, Ki-Whan Song, Jai Hyuk Song, Myungsuk Kim, Woo Young Choi,
... flash manufacturing process, thousands of internal electronic fuses (eFuse) are tuned in order to optimize performance and ... DL) and genetic algorithms (GA) to automatically tune eFuse values. Using state-of-the-art triple-level ... turnaround time (TAT) by 70% compared with manual eFuse tuning.
Tópico(s): Cellular Automata and Applications
2021 - | Proceedings - International Symposium for Testing and Failure Analysis
Gyu-Sam Cho, Meiying Jin, Mincheol Kang, Ji-Hye Jang, Pan-Bong Ha, Young‐Hee Kim,
... 외부 프로그램 전압으로 프로그램 가능한 로직 공정 기반의 eFuse OTP 셀을 제안하였다. 기존의 eFuse OTP 메모리 셀은 eFuse의 양극 (anode)에 연결된 ... 전압강하를 거치면서 프로그램 데이터가 공급된 반면, 새롭게 제안된 eFuse 셀은 NMOS 프로그램 트랜지스터의 게이트에 프로그램 데이터가 공급되고 ... 0.15{\mu}m$ generic 공정으로 설계된 8비트 eFuse OTP IP의 레이아웃 면적은 $359.92{\times}90.98{\mu}m^2$ 이다. We propose an eFuse one-time programmable (OTP) memory cell based on ... by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided ... Source Line) connected to the anode of the eFuse going through a voltage drop of the SL ...
Tópico(s): Engineering Applied Research
2010 - | The Journal of the Korean Institute of Information and Communication Engineering
Minsung Kim, Keon-Soo Yoon, Ji-Hye Jang, Liyan Jin, Pan-Bong Ha, Young‐Hee Kim,
... 0.18{\mu}m$ 공정을 이용하여 PMIC용 32bit eFuse OTP IP를 설계하였다. eFuse 링크 아래에 N-Well을 두어 프로그램시 eFuse 링크와 p-기판의 VSS가 단락되는 문제점을 해결하였다. 그리고 ... WERP (WL Enable for Read or Program) 신호가 eFuse OTP 메모리로 바로 입력되는 경우 듀얼 포트 eFuse OTP 메모리 셀의 RWL (Read Word-Line)과 ... In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0. ... a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate ... programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit ... WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP ( ...
Tópico(s): Internet of Things and Social Network Interactions
2011 - | The Journal of the Korean Institute of Information and Communication Engineering
Young-Bae Park, Liyan Jin, In-Hwa Choi, Pan-Bong Ha, Young‐Hee Kim,
... verify-read 모드를 갖는 고신뢰성 24bit differential paired eFuse OTP 메모리를 설계하였다. 제안된 program-verify-read 모드에서는 프로그램된 eFuse 저항의 변동을 고려하여 가변 풀-업 부하(variable ... program-verify-read 모드에서 24-비트 differential paired eFuse OTP와 24-비트 듀얼 포트 eFuse OTP IP의 센싱 저항은 각각 $4k{\Omega}$ 과 $50k{\Omega}$ 으로 differential paired eFuse OTP의 센싱 저항이 작게 나왔다. In this paper, a high-reliability differential paired 24-bit eFuse OTP memory with program-verify-read mode for ... In the proposed program-verify-read mode, the eFuse OTP memory can do a sensing margin test ...
Tópico(s): Semiconductor materials and devices
2013 - | The Journal of the Korean Institute of Information and Communication Engineering
Yongxu Ren, Pan-Bong Ha, Young‐Hee Kim,
... 개발 기간을 단축하기 위해 로직 트랜지스터만 이용한 로직 eFuse (electrical Fuse) OTP IP를 설계하였다. 웨이퍼 테스트 시 ... 5V)보다 높은 2.4V의 외부 프로그램 전압을 eFuse OTP IP에만 공급하므로 eFuse OTP 이외의 다른 IP에는 소자의 신뢰성에 영향을 미치지 않으면서 eFuse OTP cell의 eFuse 링크에 높은 전압을 인가하도록 하였다. 한편 본 논문에서는 ... 프로그램 파워를 증가시키면서 디코딩 로직 회로를 저면적으로 구현한 eFuse OTP 셀을 제안하였다. 동부하이텍 $0.11{\mu}m$ CIS 공정을 이용하여 설계된 1Kb eFuse OTP 메모리 IP의 레이아웃 면적은 $295.595{\mu} ... 134mm^2$ )이다. In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP ( ... than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through ...
Tópico(s): VLSI and Analog Circuit Testing
2016 - | The Journal of the Korean Institute of Information and Communication Engineering