T. Goodman, Hiroshi Fujita, Yoshinori Murakami, A.T. Murphy,
A 181 pin Pin Grid Array (PGA) was characterized using time and frequency domain techniques to identify major sources of signal degradation. The pins, as well as a layer of plating lines that was included for electroplating the exterior metal surfaces, were found to ...
Tópico(s): Electronic Packaging and Soldering Technologies
1995 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Packaging and Manufacturing Technology Part B
John H. Lau, R. Subrahmanyan, D. Rice, S. Erasmus, C. Li,
... through-hole (PTH) copper pads/barrels of a pin-grid array (PGA) assembly under thermal cycling conditions have been determined in the present study. There are two major systems of thermal stresses/strains acting at the solder joint and copper. One is the transverse shear and vertical normal stress/strain due to the local thermal expansion mismatch between the pin, solder, copper, and FR-4. The other is ...
Tópico(s): Mechanical stress and fatigue analysis
1991 - ASM International | Journal of Electronic Packaging
S. -S. Chen, J. -J. Chen, Chia‐Chun Tsai, Sao‐Jie Chen,
A pin grid array (PGA) package router is described. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to- ...
Tópico(s): Electromagnetic Compatibility and Noise Suppression
1999 - | IEE Proceedings - Computers and Digital Techniques
... mutual inductance of various electrical paths in a pin-grid array (PGA) or a chip carrier package is described. An N*N inductance matrix is generated for a package, where N is determined by the number of pins, power, and ground planes. Theory, algorithms, and software ...
Tópico(s): Electronic Packaging and Soldering Technologies
1990 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Hybrids and Manufacturing Technology
Imran Ali Chaudhry, Fred Barez,
... neck break problem in a cavity-down plastic pin grid array (PPGA) packages with a specific range of parameters ...
Tópico(s): Electrostatic Discharge in Electronics
1998 - ASM International | Journal of Electronic Packaging
Yuanliang Li, Teong-Guang Yew, Chee Yee Chung, D.G. Fugueroa,
... package that we will discuss is the Plastic Pin Grid Array (PPGA) package for Intel's CPU. Through the ... that we will discuss is the Flip Chip Pin Grid Array (FC-PGA) package, which is for Intel's ...
Tópico(s): Electronic Packaging and Soldering Technologies
2000 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Advanced Packaging
... chip carriers. This encapsulant has been implemented on pin grid array (PGA) ceramic carriers and on peripheral leaded surface ... the metal caps that were used on the pin grid array ceramic carriers or to the ceramic cap that ...
Tópico(s): Silicone and Siloxane Chemistry
1994 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Packaging and Manufacturing Technology Part A
... gains of miniaturization resulting from IC advances. A pin-grid array package with leads protruding from the bottom, can ... leaded chip carriers, leadless ceramic chip carriers, and pin-grid arrays are covered. It is pointed out that if ...
Tópico(s): Electromagnetic Compatibility and Noise Suppression
1985 - Institute of Electrical and Electronics Engineers | IEEE Spectrum
John H. Lau, S. Leung, R. Subrahmanyan, D. Rice, S. Erasmus, Chun Li,
... and plated‐through hole copper pads/barrels of pin grid array assemblies under rework condition has been determined by ...
Tópico(s): Aluminum Alloys Composites Properties
1991 - Emerald Publishing Limited | Circuit World
While primary thermal stress analysis of pin grid arrays considers a nonflexible card and module delineating the structure, in this paper we consider the stress relief (resulting in a “secondary” force system) afforded by bending and stretching of the delineating plates. The primary axial force F, plate moments, M1, M2, and shear V are considered acting in radial planes, and the secondary pin forces P are solved by stipulating compatibility of deformations at the two pin ends. A collocation technique is used to evaluate the plate ...
Tópico(s): Metal Forming Simulation Techniques
1992 - ASM International | Journal of Electronic Packaging
... three-dimensional finite element model of a plastic pin grid array (PPGA) with an internal heat slug has been ...
Tópico(s): 3D IC and TSV technologies
1993 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Hybrids and Manufacturing Technology
The role of the solder joint as an elastic foundation is investigated first for structural analysis of the pin. Failure mechanisms are discussed. For various pin cross sections, guidelines for computing the foundation constant by analytical and finite element methods are established. Exact expression are derived for the pin stress. The solder stress (radial pressure or tension) is found by an approximate contact analysis. Elasto-plastic pin analysis, for excessive thermal mismatch, is effected by ...
Tópico(s): Adhesion, Friction, and Surface Interactions
1992 - ASM International | Journal of Electronic Packaging
K. Otsuka, Yasuda Takeo, Teikichi Yamada, Seiji Kuroda, Hideki Tachi,
... reliability with pin counts over 100 pins. Plastic pin-grid-array packages with pin-embedded printed circuit boards have been previously reported ...
Tópico(s): Recycling and Waste Management Techniques
1987 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Hybrids and Manufacturing Technology
A. Hasan, A. Sarangi, Chris Baldwin, Robert Sankman, G. Taylor,
... land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor with ...
Tópico(s): VLSI and FPGA Design Techniques
2001 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Advanced Packaging
H.L. Kalter, Peter Coppens, W.F. Ellis, J.A. Fifield, D.J. Kokoszka, T.L. Leasure, Christopher P. Miller, Q. Nguyen, R.E. Papritz, Caitlyn Patton, J. Poplawski, S. W. Tomashot, W.B. van der Hoeven,
... package options include a 500-mil/SUP 2/ pin grid array module with 23 pins, and a 22 pin or 26 pin 300- ...
Tópico(s): VLSI and Analog Circuit Testing
1985 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
... and leaded full array chip carriers such as pin grid array, we applied the same concept with a Capacitor ...
Tópico(s): Electronic Packaging and Soldering Technologies
1983 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Hybrids and Manufacturing Technology
T. Tanimori, A. Ochi, S. Minami, T. Nagae,
... pitch. The MSGC was mounted on a large Pin Grid Array (PGA) package having more than 500 pins, which allowed us to readily connect a large ...
Tópico(s): Atomic and Subatomic Physics Research
1996 - Elsevier BV | Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment
J.J. Liu, Brian P. Riely, P. Shen, Naresh C. Das, P. G. Newman, Wen‐Hao Chang, George J. Simonis,
... chip bonded onto sapphire substrates and mounted in pin-grid-array packages as optical transmitter arrays. By using the ...
Tópico(s): Semiconductor Quantum Structures and Devices
2002 - Institute of Electrical and Electronics Engineers | IEEE Photonics Technology Letters
Wulf Knausenberger, N. Teneketges,
... the following IC package options: 1) through hole pin grid array, 2) surface mount pad grid array, and 3) ...
Tópico(s): VLSI and FPGA Design Techniques
1983 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Hybrids and Manufacturing Technology
E. M. Mohammed, Thomas P. Thomas, Daoqiang Lu, Henning Braunisch, Steven N. Towle, B. C. Barnett, Ian A. Young, Gilroy Vandentop,
... heterogeneously integrated on a standard microprocessor flip-chip pin grid array (FCPGA) substrate. The CMOS transceiver chip from 0. ...
Tópico(s): 3D IC and TSV technologies
2004 - SPIE | Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
M. Tatsuki, Shigeaki Kato, M. Okabe, Hideki Yakushiji, Y. Kuramitsu,
... CAD system and mounted on a 148-pin pin-grid array package. The multiplication time is 8.3 ns.
Tópico(s): Advancements in Semiconductor Devices and Circuit Design
1986 - Institute of Electrical and Electronics Engineers | IEEE Journal of Solid-State Circuits
Tien‐Yu Tom Lee, M. Mahalingam,
... limits of a flip chip package. A plastic, pin grid array (PGA) package with direct chip attach (DCA) interconnect ...
Tópico(s): Silicon Carbide Semiconductor Technologies
1997 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Packaging and Manufacturing Technology Part B
J.J. Barrett, T. Hayes, Richard L. Doyle, S. Cian Ó Mathúna, Takatoshi Yamada, A. Boetti,
... of ceramic quad flat pack (CQFP) and ceramic pin grid array (CPGA) packages; numerical prediction and practical measurement of electrical parasitics of CQFP and CPGA packages; quality and reliability testing of CQPF and CPGA packages; and quality and reliability testing of 20- and 25-mil pitch surface-mount solder assemblies of high-pin-count CQFP packages assembled on printed circuit boards. >
Tópico(s): Silicon Carbide Semiconductor Technologies
1992 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Hybrids and Manufacturing Technology
Chia‐Chun Tsai, Chwan-Ming Wang, Sao‐Jie Chen,
... wire bonded onto the multilayer substrates of a pin grid array (PGA) package, a three-step net-even-wiring system (NEWS) is proposed to complete the routing of the bond pads to the corresponding grid pins on one or more layers. First, we performed ...
Tópico(s): VLSI and Analog Circuit Testing
1998 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
G.B. Kromann, Ray Gerke, Wayne Wei-Xi Huang,
... presented. In contrast to a 51 mm, wirebond pin-grid array package (PGA), the C4/CBGA package offers several ...
Tópico(s): Electronic Packaging and Soldering Technologies
1996 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Packaging and Manufacturing Technology Part B
Daryl Dagel, William D. Cowan, Olga B. Spahn, Grant D. Grossetete, Alejandro J. Griñe, Michael Shaw, Paul Resnick, Bernhard Jokiel,
... aperture. Devices were packaged in 208 and 256 pin-grid arrays and driven by a compact control board designed ...
Tópico(s): Advanced Surface Polishing Techniques
2006 - Institute of Electrical and Electronics Engineers | Journal of Microelectromechanical Systems
Y. Hiruta, N. Hirano, Y. Yamaji, M. Mukai, Yoshiki Motoyama, R. Homma, J. Ohno, T. Sudô,
A high-pin-count, high-performance pin grid array (PGA) has been developed for future ASIC devices using half-micron BiCMOS technology and having a maximum usable gate count of 300k. The package has been designed with due consideration of all package functions, electrical, thermal, and mechanical. A surface mount type pin joint was adopted to realize high wiring density on the printed wiring board. The package has 820 pins with a 50-mil pitch ...
Tópico(s): VLSI and FPGA Design Techniques
1993 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Hybrids and Manufacturing Technology
... mm by 15.4-mm die. The plastic pin grid array (PPGA) package supplied the required current and maintained ...
Tópico(s): Heat Transfer and Optimization
1993 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components Hybrids and Manufacturing Technology
J.J. Liu, K. Olver, M. Taysing-Lara, Terrence Taylor, Wen-Hsin Chang, S. C. Horst,
... printed circuit board (PCB) or in 68-pin pin-grid-array (PGA) packages. The transparent sapphire substrate allowed optical ...
Tópico(s): Molecular Junctions and Nanostructures
2003 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Components and Packaging Technologies
John H. Lau, Walter Dauksher, Joe Smetana, Rob Horsley, Dongkai Shangguan, Todd Castello, Irv Menis, Dave Love, Bob Sullivan,
... finite element modelling. The packages were a 256‐pin plastic ball grid array (PBGA), a 388‐pin PBGA, and a 1657‐pin ceramic column grid array. Emphasis was placed on the determination of the ...
Tópico(s): Aluminum Alloy Microstructure Properties
2004 - Emerald Publishing Limited | Soldering and Surface Mount Technology