Enfang Cui, Tianzheng Li, Wei Qian,
RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions. Nowadays, RISC-V is a popular ISA for embedded processors. However, ... is still a gap between the capabilities of RISC-V and the requirements of various emerging computing scenarios (e.g., artificial intelligence, cloud computing). Recently, the RISC-V standards organization has continuously introduced new ISA extensions ...
Tópico(s): Interconnection Networks and Systems
2023 - Institute of Electrical and Electronics Engineers | IEEE Access
Produção Nacional
Revisado por pares
Benjamin W. Mezger, Douglas A. Santos, Luigi Dilillo, Cesar Albenes Zeferino, Douglas R. Melo,
RISC-V is a novel open instruction set architecture that supports multiple platforms while maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has been increasing in the last years, given ... chains and operating systems already have support for RISC-V. However, although many works have been exploring the RISC-V software ecosystem, no work that raised the current state of software support for RISC-V is available. In this context, this survey reviews ... introduced in the last years to understand the RISC-V's software ecosystem and its usage in both ...
Tópico(s): Parallel Computing and Optimization Techniques
2022 - Institute of Electrical and Electronics Engineers | IEEE Access
Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti,
... architecture. Two technologies of interest are Posit and RISC-V. Posit was introduced in mid-2017 as a viable alternative to IEEE-754, and RISC-V provides a commercial-grade open source Instruction Set ... technologies together and propose a Configurable Posit Enabled RISC-V Core called PERI. The article provides insights on ... the Single-Precision Floating Point (“F”) extension of RISC-V can be leveraged to support posit arithmetic. We ... The posit FPU has been integrated with the RISC-V compliant SHAKTI C-class core as an execution ...
Tópico(s): Low-power high-performance VLSI design
2021 - Association for Computing Machinery | ACM Transactions on Architecture and Code Optimization
Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae‐Jin Lee, Seung-Yeong Lee, Jae‐Hyoung Lee, Woojoo Lee,
RISC-V has been experiencing explosive growth since its first appearance in 2011. Dozens of free and open ... this instruction set architecture have been released, and RISC-V based devices optimized for specific applications such as ... and virtual, augmented reality are emerging. As the RISC-V cores are being used in various fields, the demand for multicore platforms composed of RISC-V cores is also rapidly increasing. Although there are various RISC-V cores developed for each specific application, and it ...
Tópico(s): Interconnection Networks and Systems
2021 - Institute of Electrical and Electronics Engineers | IEEE Access
Vladimir Herdt, Rolf Drechsler,
... virtual prototyping has been introduced for the emerging RISC-V instruction set architecture (ISA) and become an important piece of the growing RISC-V ecosystem. In this paper, we present enhanced virtual prototyping solutions tailored for RISC-V. The foundation is an advanced open source RISC-V VP implemented in SystemC TLM and designed as ... of the Linux operating system. Based on the RISC-V VP, this paper also discusses advanced VP-based ... overview and perspective on advanced virtual prototyping for RISC-V.
Tópico(s): Real-Time Systems Scheduling
2021 - Springer Nature | Science China Information Sciences
Asmit De, Aditya Basu, Swaroop Ghosh, Trent Jaeger,
RISC-V is a promising open-source architecture that targets low-power embedded devices and system-on-chips ( ... practical and low-overhead security solutions in the RISC-V architecture. Programs compiled using RISC-V toolchains are still vulnerable to code injection and ... we propose two hardware-implemented security extensions to RISC-V that provides a defense mechanism against such attacks. ... overheads. We implement the proposed Canary Engine in RISC-V RocketChip with rocket custom coprocessor (RoCC). The simulation ...
Tópico(s): Radiation Effects in Electronics
2020 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nguyen My Qui, Chang Hong Lin, Poki Chen,
... instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA). Base integer RV32I and ... one obstacle of studying new ISAs, similar to RISC-V, to design VLIW microprocessors is the lack of ... used to overcome the lack of a dedicated RISC-V VLIW compiler and leverage the available RISC-V GNU toolchain. Unlike conventional VLIWs, our proposed architecture ... synthesis frequency reaches 83.739 MHz. The proposed RISC-V-based VLIW architecture obtains an average instructions per ...
Tópico(s): Interconnection Networks and Systems
2020 - Institute of Electrical and Electronics Engineers | IEEE Access
Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler,
... as an open and free instruction set architecture RISC-V is gaining huge popularity for IoT. A large ecosystem is available around RISC-V, including various RTL implementations at one end and ... this paper, we propose and implement the first RISC-V based Virtual Prototype (VP) with the goal of filling this gap. We provide a RISC-V RV32IM core, a PLIC-based interrupt controller, and ... being more accurate than existing ISSs. Finally, our RISC-V VP is fully open source to help expanding the RISC-V ecosystem and stimulating further research and development.
Tópico(s): Real-Time Systems Scheduling
2019 - Springer Science+Business Media | Lecture notes in electrical engineering
Stavros Kalapothas, Manolis Galetakis, Georgios Flamis, Fotis Plessas, Paris Kitsos,
... In particular, the reduced instruction-set computer-five (RISC-V) open standard architecture has been widely adopted by ... available implementations. The selection through a plethora of RISC-V processor cores and the mix of architectures and ... on the assessment of the ecosystem that entails RISC-V based hardware for creating a classification of system- ... domain. This study presents a quantitative taxonomy of RISC-V SoC and reveals the opportunities in future research in machine learning with RISC-V open-source hardware architectures.
Tópico(s): Advanced Memory and Neural Computing
2023 - Multidisciplinary Digital Publishing Institute | Information
Chun‐Chieh Yang, Yi-Ru Chen, Hui-Hsin Liao, Yuan‐Ming Chang, Jenq‐Kuen Lee,
... the proposed method enables a flow with the RISC-V Packed extension (P extension) in TVM. TVM, an ... growing as a key infrastructure for DL computing. RISC-V is an open instruction set architecture (ISA) with ... flexible features. The Packed-SIMD extension is a RISC-V extension that enables subword single-instruction multiple-data (SIMD) computations in RISC-V architectures to support fallback engines in AI computing. ... specific hardware such as subword SIMD instructions with RISC-V P extension. With our experiment on the Spike ...
Tópico(s): Numerical Methods and Algorithms
2022 - Association for Computing Machinery | ACM Transactions on Design Automation of Electronic Systems
Tim Fritzmann, Georg Sigl, Johanna Sepúlveda,
... this end, we present RISQ-V, an enhanced RISC-V architecture that integrates a set of powerful tightly ... of powerful hardware accelerators deeply integrated into the RISC-V pipeline. Second, we extended the RISC-V ISA with 29 new instructions to efficiently perform ... V. Compared to the pure software implementation on RISC-V, our co-design implementations show a speedup factor ... factor of 1.6 compared to the original RISC-V design, which can be considered as a moderate ...
Tópico(s): Cryptography and Data Security
2020 - | IACR Transactions on Cryptographic Hardware and Embedded Systems
Joseph K. L. Lee, Maurice Jamieson, Nick Brown, Ricardo Jesus,
Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing both hardware implementations and open source software support are still limited for vectorisation on RISC-V. This is important because vectorisation is crucial to ... RVV. This paper surveys the current state of RISC-V vectorisation as of 2023, reporting the landscape of ... the Allwinner D1 as part of the EPCC RISC-V testbed, we report the results of benchmarking the ...
Tópico(s): Interconnection Networks and Systems
2023 - Springer Science+Business Media | Lecture notes in computer science
Produção Nacional
Nicolas Lodéa, Willian Analdo Nunes, Vitor Balbinot Zanini, M. Sartori, Luciano Ost, Ney Calazans, Rafael Garibotti, César Marcon,
The adoption of RISC-V processors bloomed in recent years, mainly due to its open standard and free instruction set architecture. However, much remains ... and bug-free applications and systems based on RISC-V IP designs. This work proposes an early soft error reliability assessment of a RISC-V processor, extending the previously proposed SOFIA fault injection ... This work helps software engineers develop fault-tolerant RISC-V-based systems and applications more efficiently.
Tópico(s): Real-Time Systems Scheduling
2022 - Institute of Electrical and Electronics Engineers | IEEE Latin America Transactions
Jim Plusquellic, Donald E. Owen, Tom J. Mannos, Brian Dziki,
The RISC-V instruction set architecture open licensing policy has spawned a hive of development activity, making a range of implementations publicly available. The environments in which RISC-V operates have expanded correspondingly, driving the need for a generalized approach to evaluating the reliability of RISC-V implementations under adverse operating conditions or after normal ... faults and report execution behavior. A pair of RISC-V FI-instrumented implementations are created and configured to ...
Tópico(s): Cryptographic Implementations and Security
2021 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, Sergio Saponara,
Abstract With the arrival of the open-source RISC-V processor architecture, there is the chance to rethink ... implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up ... it is possible to vectorize posit operations on RISC-V, gaining a substantial speed-up on all the ... to achieve when we will have an open RISC-V hardware co-processor capable to operate natively with ...
Tópico(s): Digital Filter Design and Implementation
2021 - Springer Science+Business Media | Neural Computing and Applications
Bruno Sá, José Martins, Sandro Pinto,
... and evaluation of the latest version of the RISC-V hypervisor extension (H-extension v0.6.1) specification ... Bao, an open-source static partitioning hypervisor, to RISC-V. We have also extended the RISC-V platform-level interrupt controller (PLIC) to enable direct ... sourced and is currently in use by the RISC-V community towards the ratification of the H-extension ...
Tópico(s): Parallel Computing and Optimization Techniques
2021 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Computers
Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, Sergio Saponara,
... emerging in neural networks. First, there is the RISC-V open instruction set architecture (ISA) that allows a ... light). We present an extension of the base RISC-V ISA that allows the conversion between 8 or ... integration of our PPU-light inside the Ariane RISC-V core and its toolchain, showing how little it ... devoted to the PPU-light while the full RISC-V core occupies the 33% of the overall circuit ...
Tópico(s): Numerical Methods and Algorithms
2021 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Emerging Topics in Computing
Vinay Kumar, S. Deb, Naina Gupta, Shivam Bhasin, Jawad Haj-Yahya, Anupam Chattopadhyay, Avi Mendelson,
... a first-class consideration. Following the momentum behind RISC-V-based systems in the public domain, much of this effort targets RISC-V-based SoCs; most ideas, however, are independent of ... these lines in designing a secure SoC around RISC-V, named ITUS. In particular, we discuss a set ... PUF-based key management, a countermeasure methodology for RISC-V micro-architectural side-channel leakage, and an integration ...
Tópico(s): Cryptographic Implementations and Security
2020 - Springer Science+Business Media | Journal of Hardware and Systems Security
The open-source RISC-V ISA is gaining traction, both in industry and academia. The ISA is designed to scale from micro-controllers to ... thorough power, performance, and efficiency analysis of the RISC-V ISA targeting baseline "application class" functionality, i.e. ... a detailed power and efficiency analysis of the RISC-V ISA extracted from silicon measurements and calibrated simulation ... e.g. packed SIMD) can significantly boost a RISC-V core's compute energy efficiency.
Tópico(s): Interconnection Networks and Systems
2019 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Xiaoyong Xue, Chenzedai Wang, Wen-Jun Liu, Hangbing Lv, Mingyu Wang, Xiaoyang Zeng,
... a long processing time. This paper proposes an RISC-V processor with memristor-based in-memory computing (IMC) ... algorithm by virtue of the extendibility of the RISC-V instruction set architecture (ISA). Then, an RISC-V processor with area-efficient memristor-based IMC was ... limited area overhead after introducing IMC in the RISC-V processor.
Tópico(s): Caching and Content Delivery
2019 - Multidisciplinary Digital Publishing Institute | Micromachines
Stefano Di Mascio, Alessandra Menicucci, E. Gill, Gianluca Furano, Claudio Monteleone,
... present and future needs in space systems with RISC-V processors. RISC-V is an open and modular instruction set architecture, ... processors for artificial intelligence. Several solutions based on RISC-V are proposed for each of these types of ... available from literature is conducted to show that RISC-V has the potential to solve such a wide ...
Tópico(s): Spacecraft Design and Technology
2019 - American Institute of Aeronautics and Astronautics | Journal of Aerospace Information Systems
RISC-V is a promising free and open-source instruction set architecture. Most of the instruction set has ... available. In this paper we highlight features of RISC-V that are interesting for optimizing implementations of cryptographic ... the improvement that can be gained by several RISC-V extensions. These performance studies also serve to aid design choices for future RISC-V extensions and implementations.
Tópico(s): Coding theory and cryptography
2019 - Springer Science+Business Media | Lecture notes in computer science
Mate Kovač, Leon Dragić, Branimir Malnar, Francesco Minervini, Oscar Palomar, Carlos del Valle Rojas, Mauro Olivieri, Josip Knezović, Mario Kovač,
... Faust, a pipelined FPU for vector processing-capable RISC-V core developed within the European Processor Initiative (EPI) ... that was extended and redesigned to support the RISC-V Vector extension specification (RVV) 1.0 and the ... and taped out as part of Vitruvius, a RISC-V Vector Processing unit of the EPAC1.0, the ...
Tópico(s): VLSI and Analog Circuit Testing
2023 - Elsevier BV | Microprocessors and Microsystems
Produção Nacional
Revisado por pares
Douglas A. Santos, André Martins Pio de Mattos, Douglas R. Melo, Luigi Dilillo,
Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace ... features to increase their reliability. Studies on hardened RISC-V processors facing harsh radiation environments apply fault tolerance ... redundancies. In prior work, we present a hardened RISC-V System-on-Chip (SoC), which could detect and ...
Tópico(s): Advanced Battery Technologies Research
2023 - Multidisciplinary Digital Publishing Institute | Electronics
Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler,
... paper we propose μRV32 (MicroRV32) an open source RISC-V platform for education and research. μRV32 integrates several peripherals alongside a configurable 32 bit RISC-V core interconnected with a generic bus system. It ... way for advanced cross-level methodologies in the RISC-V context. Moreover, based on a readily available open ...
Tópico(s): VLSI and Analog Circuit Testing
2022 - Elsevier BV | Journal of Systems Architecture
Francesco Minervini, Oscar Palomar, Osman Ünsal, Enrico Reggiani, Josue V. Quiroga, Joan Marimon, Carlos Rojas, Roger Figueras, Abraham Ruiz, Alberto González, Jonnatan Mendoza, Ivan Vargas Valdivieso, César Alejandro Hernández, Joan Cabré, Lina Khoirunisya, Mustapha Bouhali, Julián Pavón, Francesc Moll, Mauro Olivieri, Mario Kovač, Mate Kovač, Leon Dragić, Mateo Valero, Adrián Cristal,
The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of ... comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can ...
Tópico(s): Interconnection Networks and Systems
2022 - Association for Computing Machinery | ACM Transactions on Architecture and Code Optimization
Jipeng Zhang, Junhao Huang, Zhe Liu, Sujoy Sinha Roy,
... software implementation of Saber+ on a memory-constrained RISC-V platform achieves 48% performance improvement compared with the ... performance optimizations for Saber+ on a memory-constrained RISC-V microcontroller, with merely 16KB of memory available. We ... explored. Our software implementation for Saber+ on selected RISC-V core takes just 3,809K, 3,594K, and ...
Tópico(s): Coding theory and cryptography
2022 - Institute of Electrical and Electronics Engineers | IEEE Transactions on Computers
Ahmed Kamaleldin, Diana Göhringer,
... re-usability. The recent widespread of open-source RISC-V ISA provides the potential to develop modular compute ... adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular ... core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Inter-tile communication ...
Tópico(s): Embedded Systems Design Techniques
2022 - Institute of Electrical and Electronics Engineers | IEEE Access
... agnostic vector instruction set architecture (ISA) designs, the RISC-V vector extension, and ARM's scalable vector extension ... We examine LLVM's support for both the RISC-V vector extension and traditional vector ISAs. We study ... benchmark suite to compare autovectorized to hand-vectorized RISC-V code. We use both studies to distill a ...
Tópico(s): Advanced Data Storage Technologies
2022 - Institute of Electrical and Electronics Engineers | IEEE Micro
Ivo Marques, Cristiano Rodrigues, Adriano Tavares, Sandro Pinto, Tiago Gomes,
... VA features an Arm Cortex-A9 with a RISC-V RV64GC, while Lock-VM includes an Arm Cortex-M3 along with a RISC-V RV32IMA processor. The solution explores field-programmable gate ... FPGA) technology to deploy softcore versions of the RISC-V processors, and dedicated accelerators for performing error detection ...
Tópico(s): Advanced Battery Technologies Research
2021 - Elsevier BV | Microelectronics Reliability