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A 0.18-/spl mu/m 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica

2000; Institute of Electrical and Electronics Engineers; Volume: 35; Issue: 11 Linguagem: Inglês

10.1109/4.881215

1558-173X

S. Kuge, T. Kato, K. Furutani, S. Kikuda, K. Mitsui, T. Hamamoto, J. Setogawa, K. Hamade, Yuichiro Komiya, S. Kawasaki, T. Kono, T. Amano, Takahiro Kubo, Manabu Haraguchi, Y. Nakaoka, Masatoshi Akiyama, Y. Konishi, H. Ozaki, T. Yoshihara,

VLSI and Analog Circuit Testing

A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation.