Capítulo de livro Acesso aberto Revisado por pares

Simulation of Parasitic Interconnect Capacitance for Present and Future ICs

2005; Springer Science+Business Media; Linguagem: Inglês

10.1007/11428831_75

ISSN

1611-3349

Autores

Grzegorz Tosik, Zbigniew Lisik, Małgorzata Langer, Janusz Woźny,

Tópico(s)

Electrostatic Discharge in Electronics

Resumo

The performance of modern integrated circuits is often determined by interconnect wiring requirements. Moreover, continuous scaling of VLSI circuits leads to an increase in the influence of interconnects on system performance. It is desired therefore, to calculate accurately its parasitic components, particularly wiring capacitance. In order to recognize which one from the most popular empirical approaches gives the evaluation of the total capacitance that suits to the real capacitance of the interconnect line, the numerical simulations based on the numerical solving of Maxwell equations have been employed.

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