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A scalable multi-discipline, multiple-processor scheduling framework for IRIX

1995; Springer Science+Business Media; Linguagem: Inglês

10.1007/3-540-60153-8_22

1611-3349

James M. Barton, Nawaf Bitar,

Embedded Systems Design Techniques

This document describes the processor scheduling framework implemented in the Silicon Graphics IRIX Version 5 operating system. This framework provides the standard features and behavior expected of any UNIX time-sharing system, while adding support for four additional disciplines: a fast-response scheme for lowlatency real-time computing, a time-based regime for throughputoriented real-time computing, a multi-thread scheme for parallel computing applications, and several flavors of batch processing. In addition, the scheduling framework adds the notions of processor cache affinity, which attempts to take advantage of data already fetched into a particular processor cache, and processor sets, which allow an additional level of scheduling control on a per-processor basis. These features have been successfully deployed in production environments on machines ranging from single-processor desktop workstations to high-performance supercomputing multi-processors.