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6×86: the Cyrix solution to executing ×86 binaries on a high performance microprocessor

1995; Institute of Electrical and Electronics Engineers; Volume: 83; Issue: 12 Linguagem: Inglês

10.1109/5.476082

1558-2256

S. McMahan, M. Bluhm, R.A. Garibay,

Interconnection Networks and Systems

With the 6/spl times/86 microprocessor, Cyrix's design team demands optimum functionality and performance at an acceptable cost. Cyrix maintains that the way to get high performance is to keep larger units of processing together and to incorporate as much concurrency of execution as possible. To do the former, the microprocessor attempts to keep together all parts of an /spl times/86 instruction as it passes through its seven processing steps. To do the latter, it attempts to initiate the processing of two /spl times/86 instructions each cycle, and pipelines the processing of each instruction in seven stages. Most of this paper deals with issues involving keeping these seven stages of the two pipelines busy so the microprocessor can attempt to approach the twofold increase in performance that is made possible by the underlying structure.