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Low power logic design using push-pull pass-transistor logics

1998; Taylor & Francis; Volume: 84; Issue: 5 Linguagem: Inglês

10.1080/002072198134571

1362-3060

Woo Hyun Paik, Hoon Jae Ki, Soo Won Kim,

Advancements in PLL and VCO Technologies

This paper describes a new pass-transistor logic family, named PPL (Push-pull Pass-transistor Logic), for low power which restores outputs by the push-pull operation. Using Push-pull Pass-transistor Logics, 40-stage full adder chain and 8-bit multiplier circuits are designed and fabricated in a 0.8µm CMOS process technology. The PPL achieves 36.4ns delay with the power consumption of 18mW/100MHz in the full adder chain and 112MHz speed with 13.4mW/ 50MHz power dissipation in the multiplier.