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A compiler with scheduling for a specialized synchronous multiprocessor system

1991; Springer Science+Business Media; Linguagem: Inglês

10.1007/3-540-53669-8_79

1611-3349

Petr Kroha, Peter Fritzson,

Interconnection Networks and Systems

This paper presents an algorithm for scheduling parallel activities in a specialized synchronous multiprocessor system. The algorithm is being implemented as a part of a cross-compiler for an extended parallel Single Instruction Computer (SIC). A SIC machine may contain multiple arithmetic processors, each associated with certain addresses in the address space. The scheduling cross-compiler initially derives a schedule including information about the number and types of processors necessary for the highest possible degree of parallelism for the code in each basic block. If too few arithmetic processors are available, a schedule for a smaller number of processors can be generated. Code generation and scheduling is presented for a one page program example in Pascal. For this example, a speedup of a factor of seven was obtained for the multiprocessor system, compared to the Intel 80286 processor, and assuming the same clock cycle time.