Determining optimal switching speed for memristors in neuromorphic system
2015; Institution of Engineering and Technology; Volume: 51; Issue: 21 Linguagem: Inglês
10.1049/el.2015.1145
ISSN1350-911X
Autores Tópico(s)CCD and CMOS Imaging Sensors
ResumoElectronics LettersVolume 51, Issue 21 p. 1637-1639 Bioinspired technologyFree Access Determining optimal switching speed for memristors in neuromorphic system C. Yakopcic, Corresponding Author C. Yakopcic cyakopcic1@udayton.edu Department of Electrical and Computer Engineering, University of Dayton, 300 College Park, Dayton, 45409 Ohio, USASearch for more papers by this authorT.M. Taha, T.M. Taha Department of Electrical and Computer Engineering, University of Dayton, 300 College Park, Dayton, 45409 Ohio, USASearch for more papers by this author C. Yakopcic, Corresponding Author C. Yakopcic cyakopcic1@udayton.edu Department of Electrical and Computer Engineering, University of Dayton, 300 College Park, Dayton, 45409 Ohio, USASearch for more papers by this authorT.M. Taha, T.M. Taha Department of Electrical and Computer Engineering, University of Dayton, 300 College Park, Dayton, 45409 Ohio, USASearch for more papers by this author First published: 01 October 2015 https://doi.org/10.1049/el.2015.1145Citations: 18AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract As non-volatile memory based on resistive switching becomes more mature, memristor devices with very fast switching times are becoming more prominent. However, this reported work shows that memristor devices with slow switching times (of about 10 µs) are more appropriate for use in neuromorphic systems. This is done by modelling a series of memristors that differ in their switching time. Simulation of a memristor-based neuromorphic circuit is performed using each of these modelled devices. Devices with a high switching speed require unrealistically small voltage pulses to incrementally change the memristor resistance. Introduction Memristors [1] have received significant attention as a potential building block for neuromorphic systems [2-4]. Physical memristors [5] can be laid out in a high density grid known as a crossbar [6]. Using this layout, memristors have the potential to be fabricated with a synaptic density greater than that of brain tissue [4]. These devices can be used to produce high density, extreme low-power, neuromorphic hardware capable of performing many parallel multiply-add operations in the analogue domain. One of the limitations of these systems is the current state of memristor technology. As memristors for non-volatile memory systems [7] have matured, the technology has forced the development of a memristor [8] that can switch its entire resistance range as quickly as possible. However, neuromorphic circuits work by storing a specific set of weights that for the most part remain unchanged during normal operation. A common approach for the development of memristor-based neuromorphic circuits is to use the continuous resistance range of a memristor to store the weight matrix produced by a learning algorithm. In this case, it is more important to be able to slowly arrive at a specific resistance though a number of feedback controlled voltage pulses [2]. If the switching speed of the memristor device is too high, tuning to a specific resistance will require unrealistically small voltage pulses (of the order of 10 ps). Therefore, programming the intermediate states of most existing memristor devices will be very difficult, if not impossible. Through simulation, this Letter shows that there are two ways to reduce the amount of pulse-induced switching in memristors. The first study shows that the switching time of a memristor device is longer if the voltage magnitude of the write pulse is reduced. However, since memristors often exhibit a threshold voltage that must be surpassed for a resistance change to occur, there is a limit to how much the voltage can be reduced. A much more effective way to reduce switching time is to fabricate a memristor device that physically takes a longer time to switch from its minimum to maximum resistance. Our results show that developing a slower device will have a much greater impact on reducing switching time when compared with lowering the input voltage. Using both the slow memristor device and a low write voltage (relative to the memristor threshold voltage), a neuromorphic circuit was trained successfully with significantly longer pulse widths (of the order of 10 ns). The result of these experiments demonstrates a necessity for the production of memristor devices with a much longer switching time. Memristor switching time analysis One approach to design a memristor based neuromorphic system is to use specific points in the memristor resistance range to represent synaptic weights between the input and output neurons. The slower the memristors switch, the easier it will be to push their resistances to the desired values. The memristor model in [9] was used to study how the switching time of a memristor could be reduced. Reducing the voltage magnitude of the write pulse is one possible way to reduce the switching speed of a memristor device. However, the write voltage can only be lowered so much before sources of noise stop the write voltage from being reliably above the write threshold. For example, it would not be a robust design to have a write voltage of 4.05 V with a threshold of 4 V. Therefore, we assumed that the minimum write voltage for a memristor with a 4 V threshold should be about 4.5 V. Fig. 1 shows that lowering the write pulse voltage will reduce the amount of change in the memristor state variable. The value of the state variable [9] must fall between 0 and 1, and it represents the change in the physical properties of the memristor that is inversely proportional to the dynamic resistance within a memristor. Reducing the write voltage from 7 to 4.5 V increases the total switching time from 2 to about 50 ns (these large write voltages are used to match the device properties found in [10]). Fig 1Open in figure viewerPowerPoint Impact that reducing write voltage has on memristor switching for 10 ns pulse. Model parameters are based on device in [10]: Vp = 4 V, Vn = 4 V, Ap = 816 000, An = 816 000, xp = 0.985, xn = 0.985, αp = 0.1, αn = 0.1, a1 = 1.6 × 10−4, a2 = 1.6 × 10−4, b = 0.05 and x0 = 0.01 Fig. 1 shows that the amount of switching due to a 10 ns pulse can be slightly reduced by reducing the voltage magnitude. However, neuromorphic systems require a significantly smaller amount of resistance change, so the memristor model characteristics were altered as shown in Table 1. Devices 2–4 in Table 1 are based on Device 1, but had their switching speed reduced by factors of 10. If devices are developed with these slower switching times, it will be possible to greatly reduce switching speed as shown in Fig. 2. The state variable of Device 4 only changes by 0.03% with the application of a 10 ns pulse, as opposed to the 30% change seen in Device 1. Table 1. Device models that were developed with different switching times Device option Switching speed (Ap and An values in the memristor model) 1 816 000 2 81 600 3 8160 4 816 Fig 2Open in figure viewerPowerPoint Impact different switching times have on state change with application of 10 ns pulse with magnitude of 4.5 V Neuromorphic simulation The schematic in Fig. 3a shows our approach for developing a memristor-based neuromorphic circuit [11]. This example shows two data inputs in addition to a high and low bias input. Each signal input is connected to the positive and negative comparator input through a grid of memristors. The neuron outputs in our study had thresholded outputs, so a comparator was used. Two memristors are required to represent a single synaptic weight, as this allows for each data input to have either a positive or a negative impact on the column voltage (DPj). The multilayer circuit in Fig. 3 was trained to learn an xor function using the concurrent learning algorithm [12] (a supervised learning algorithm that is designed to have a minimal hardware footprint). This circuit was trained using both a 6 and a 4.5 V write pulse magnitude. In each case, the minimum pulse width required to successfully train the circuit was recorded. This pulse width essentially relates to how small a resistance is required for the network to successfully converge to a solution (see Fig. 4). Table 2 shows that the minimum pulse width required can be increased by a factor of 10 if the voltage magnitude is lowered from 6 to 4.5 V. Fig 3Open in figure viewerPowerPoint Schematic for neural network that was simulated, and equivalent neural networka Schematic for neural network circuit that was simulated b Equivalent neural network Fig 4Open in figure viewerPowerPoint Plot that displays absolute error in system over training process. This shows circuit in Fig. 3 converging to solution after 74 epochs Table 2. Impact of write voltage on switching time using Device 1 Switching voltage (V) Minimum required training pulse width for successful learning (ps) 6 1 4.5 10 A minimum training pulse width of 10 ps would still require complex and high speed training hardware. Therefore, the neuromorphic circuit was trained using each of the slower devices in Table 1. Table 3 shows how the minimum pulse width required to learn the xor function increases as the device switching time is reduced. The slowest device that was tested (Device 4) shows that the circuit can learn xor with a minimum pulse width of 10 ns, a much easier pulse to generate. This equates to a device that has a total switching time of 10 µs. Therefore, a device with a total switching time of 10 µs will be sufficient for neuromorphic systems. Table 3. Impact of device speed on switching time with a 4.5 V write Device option Minimum required training pulse width for successful learning (ns) 1 0.01 2 0.1 3 1 4 10 Conclusion This Letter provides a demonstration that shows slower memristor devices would be ideal for use in neuromorphic applications. The precision required to solve complex nonlinearly separable problems requires a significant amount of control over the range of resistance values that a memristor is capable of producing. Therefore, we show that production of physical memristor devices that take at least 10 µs to switch from their minimum to maximum resistance will be very beneficial to the development of memristor-based neuromorphic processors. References 1Chua, L.O.: ‘Memristor – the missing circuit element’, IEEE Trans. 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