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A Configurable and Low-Power Mixed Signal SoC for Portable ECG Monitoring Applications

2013; Institute of Electrical and Electronics Engineers; Volume: 8; Issue: 2 Linguagem: Inglês

10.1109/tbcas.2013.2260159

1940-9990

Hye Jung Kim, Sun Young Kim, Nick Van Helleputte, Antonio Artés‐Rodríguez, Mario Konijnenburg, Jos Huisken, Chris Van Hoof, Refet Fırat Yazıcıoğlu,

Advancements in PLL and VCO Technologies

This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 μm CMOS process and consumes 32 μW from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.