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A 27-mW 3.6-Gb/s I/O Transceiver

2004; Institute of Electrical and Electronics Engineers; Volume: 39; Issue: 4 Linguagem: Inglês

10.1109/jssc.2004.825259

1558-173X

K.-L.J. Wong, Hamid Hatamkhani, Mozhgan Mansuri, Chih-Kong Ken Yang,

Semiconductor Lasers and Optical Devices

This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.