Portal de Periódicos da CAPES

<title>Wafer flatness modeling for scanning steppers</title>

1996; SPIE; Volume: 2725; Linguagem: Inglês

10.1117/12.240143

1996-756X

Randal K. Goodall, Howard R. Huff,

3D IC and TSV technologies

Model-based analysis is used to explain previous observations regarding the distributional form and numeric relationships of several key lithographic flatness quality metrics for silicon wafers. The dominant relationships are controlled by longer wavelength (tens of millimeters) surface topography, while the distribution shapes are controlled by shorter wavelength (few millimeters) topography. A lithographic flatness modeling framework is introduced which can provide guidance for specification of silicon wafer flatness for ULSI IC products. New site flatness models show that, compared to a full-field stepper, a scanning stepper can effect improved flatness performance from wafers of similar quality.