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A single-chip IBM System/390 floating-point processor in CMOS

1992; IBM; Volume: 36; Issue: 4 Linguagem: Inglês

10.1147/rd.364.0733

2151-8556

S. Dao-Trong, Klaus Helwig,

Parallel Computing and Optimization Techniques

A floating-point processor with the IBM System/390® architecture is implemented in one CMOS VLSI chip containing over 70,000 cells (equivalent inverters), using a transistor channel length of 0.5 µm. All floating-point instructions are hard-wired, including the binary integer multiplications. The chip is implemented in a 1-µm technology with three layers of metal. All circuits are realized in standard cells except for a floating-point register and a multiplier array macro, which are custom designed to save chip area. Instructions are performed in a five-stage pipeline with a maximum operating frequency of 37 MHz. The chip measures 12.7 mm × 12.7 mm, and dissipates 2 W. It is part of the chip set which forms the core of the IBM Enterprise System/9000™ Type 9221 entry-level models.