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Cache memories for PDP-11 family computers

1976; ACM SIGARCH; Volume: 4; Issue: 4 Linguagem: Inglês

10.1145/633617.803574

1943-5851

William D. Strecker,

Interconnection Networks and Systems

This paper gives a summary of the research which led to the design of the cache memory in the DEC PDP-11/70. The concept of cache memory is introduced together with its major organizational parameters: size, associativity, block size, replacement algorithm, and write strategy. Simulation results are given showing how the performance of the cache varies with changes in these parameters. Based on these simulation results the design of the 11/70 cache is justified.