Optimization of CVD dielectric process to achieve reliable ultra low-k air gaps
2002; Elsevier BV; Volume: 60; Issue: 1-2 Linguagem: Inglês
10.1016/s0167-9317(01)00590-1
ISSN1873-5568
AutoresV. Arnal, Joaquin Torres, Jean–Philippe Reynard, Philippe Gayet, C. Vérove, M. Guillermet, P. Spinelli,
Tópico(s)Anodic Oxide Films and Nanostructures
ResumoThe capability of CVD silicon oxide has been studied to achieve a controlled air gap between copper interconnects for sub-quarter micron CMOS technologies. Several deposition parameters have been investigated and their influence on air gap morphology and electrical performances are shown in this paper. A reliable process has been obtained from these experiments. The parasitic capacitance between lines is reduced by half using SiO2 air gap material.
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