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Extending Magny-Cours Cache Coherence

2011; Institute of Electrical and Electronics Engineers; Volume: 61; Issue: 5 Linguagem: Inglês

10.1109/tc.2011.65

2326-3814

Alberto Ros, Blas Cuesta, Ricardo Fernández‐Pascual, Marı́a Engracia Gómez Requena, Manuel E. Acacio, Antonio Robles, José M. Garcı́a, J. Duato,

Advanced Memory and Neural Computing

One cost-effective way to meet the increasing demand for larger high-performance shared-memory servers is to build clusters with off-the-shelf processors connected with low-latency point-to-point interconnections like HyperTransport.Unfortunately, HyperTransport addressing limitations prevent building systems with more than eight nodes.While the recent High-Node Count HyperTransport specification overcomes this limitation, recently launched twelve-core Magny-Cours processors have already inherited it and provide only 3 bits to encode the pointers used by the directory cache which they include to increase the scalability of their coherence protocol.In this work, we propose and develop an external device to extend the coherence domain of Magny-Cours processors beyond the 8-node limit while maintaining the advantages provided by the directory cache.Evaluation results for systems with up to 32 nodes show that the performance offered by our solution scales with the number of nodes, enhancing the directory cache effectiveness by filtering additional messages.Particularly, we reduce execution time by 47 percent in a 32-die system with respect to the 8-die Magny-Cours configuration.