Design of 1-Kb eFuse OTP Memory IP with Reliability Considered
2011; Institute of Electronics Engineers of Korea; Volume: 11; Issue: 2 Linguagem: Inglês
10.5573/jsts.2011.11.2.088
ISSN2233-4866
AutoresJeong-Ho Kim, Du-Hwi Kim, Liyan Jin, Pan-Bong Ha, Young‐Hee Kim,
Tópico(s)VLSI and Analog Circuit Testing
ResumoIn this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the nonprogrammed eFuse is reduced from 728 ㎂ to 61 ㎂ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 ㏀ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).
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