Portal de Periódicos da CAPES

Implementing FFT-based digital channelized receivers on FPGA platforms

2008; Institute of Electrical and Electronics Engineers; Volume: 44; Issue: 4 Linguagem: Inglês

10.1109/taes.2008.4667732

2371-9877

Miguel A. Sanchez, Mario Garrido, Marisa López‐Vallejo, Jesús Grajal,

Advancements in PLL and VCO Technologies

This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed in depth, revealing interesting implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.