Portal de Periódicos da CAPES

Fault Tolerance Techniques for Array Structures Used in Supercomputing

1986; IEEE Computer Society; Volume: 19; Issue: 2 Linguagem: Inglês

10.1109/mc.1986.1663151

1558-0814

Negrini, Сами, Stefanelli,

Embedded Systems Design Techniques

In this article, the authors deal with the standardized class of parallel machines. Fast, highly parallel, dedicated array units are well suited to VLSI or even WSI implementation because of the extreme regularity of their architecture and their interconnection locality. Given these attributes, it is reasonable, as H.T. Kung suggests, to look for algorithms inherently suited to such arrays (signal-processing algorithms, for instance, fall within this class). Among the most attractive examples of array units discussed in the literature are the chip structure and, most notably, the class of systolic arrays. On such architectures it is possible to activate a wavefront computation mode, in which computation propagates along one direction only for the various interconnection axes. The systems considered here are, then, regular interconnections of processing elements (cells), with information flowing in one direction only along all interconnection lines. The authors require that no memory devices be present in the array, with the possible exception of local ''service'' memories (for example, registers in serial arithmetic units). This limited use of memory elements is acceptable for attached processors that generally communicate by means of I/O lines with the main memories.