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A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits

1995; Institute of Electrical and Electronics Engineers; Volume: 30; Issue: 4 Linguagem: Inglês

10.1109/4.375970

1558-173X

S. Tachibana, Hiroyoshi Higuchi, K. Takasugi, K. Sasaki, Toshiaki Yamanaka, Y. Nakagome,

Low-power high-performance VLSI design

The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-/spl mu/m CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns. >