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Design Trade-Offs in VAX-11 Translation Buffer Organization

1981; IEEE Computer Society; Volume: 14; Issue: 12 Linguagem: Inglês

10.1109/c-m.1981.220301

1558-0814

Mahadev Satyanarayanan, Dileep Bhandarkar,

VLSI and Analog Circuit Testing

A major feature of the VAX-11 is its large virtual address space. This trace-driven simulation scheme evaluates address translation hardware that supports this feature cost-effectively.