A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption
2007; Institute of Electrical and Electronics Engineers; Linguagem: Inglês
10.1109/isscc.2007.373607
ISSN2376-8606
AutoresYutaka Yoshida, T. Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara,
Tópico(s)Interconnection Networks and Systems
ResumoA 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm 2 die achieves a floating-point performance of 16.8GFLOPS
Referência(s)