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A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method

2015; Institute of Electrical and Electronics Engineers; Volume: 62; Issue: 5 Linguagem: Inglês

10.1109/tcsii.2014.2387531

1558-3791

Jong‐Boo Kim, Seong‐Kwan Hong, Oh‐Kyong Kwon,

Neuroscience and Neural Engineering

This brief presents a low-power CMOS image sensor with 14-bit column-parallel two-step (TS) successive approximation (SA) analog-to-digital converters (ADCs). The proposed TS SA ADC adopts a pseudomultiple sampling method to reduce the power consumption and the area. For implementing the 14-bit ADC, it only uses a capacitor digital-to-analog converter of 6 bits rather than 14 bits. The multiple sampling also suppresses the noise of a pixel and a column-parallel ADC. The image sensor is fabricated by using the 0.13-μm CMOS process. The measurement results show that the temporal noise is 82.7 μVrms, and the power consumption is 55.1 μW for one column ADC with a programmable gain amplifier. With the digital correlated double sampling and the TS calibration method, the proposed ADC achieves the column fixed-pattern noise of 0.98 LSB and a differential nonlinearity of +0.99/-0.90 LSB.