Produção Nacional
Revisado por pares
Single‐phase ac–dc–ac multilevel five‐leg converter
2014; Institution of Engineering and Technology; Volume: 7; Issue: 11 Linguagem: Inglês
10.1049/iet-pel.2013.0833
ISSN1755-4543
AutoresAyslan C. N. Maia, Cursino B. Jacobina,
Tópico(s)Silicon Carbide Semiconductor Technologies
ResumoIET Power ElectronicsVolume 7, Issue 11 p. 2733-2742 ArticleFree Access Single-phase ac–dc–ac multilevel five-leg converter Ayslan Caisson Norões Maia, Ayslan Caisson Norões Maia Electrical Engineering Department (DEE), Federal University of Campina Grande (UFCG), 58.429-900 Campina Grande, PB, BrazilSearch for more papers by this authorCursino Brandão Jacobina, Corresponding Author Cursino Brandão Jacobina [email protected] Electrical Engineering Department (DEE), Federal University of Campina Grande (UFCG), 58.429-900 Campina Grande, PB, BrazilSearch for more papers by this author Ayslan Caisson Norões Maia, Ayslan Caisson Norões Maia Electrical Engineering Department (DEE), Federal University of Campina Grande (UFCG), 58.429-900 Campina Grande, PB, BrazilSearch for more papers by this authorCursino Brandão Jacobina, Corresponding Author Cursino Brandão Jacobina [email protected] Electrical Engineering Department (DEE), Federal University of Campina Grande (UFCG), 58.429-900 Campina Grande, PB, BrazilSearch for more papers by this author First published: 01 November 2014 https://doi.org/10.1049/iet-pel.2013.0833Citations: 19AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Abstract In this study, a multilevel five-leg single-phase ac–dc–ac converter and its generalisation are presented. The converter is suitable to be used as an uninterrupted power supply or a unified power quality conditioner without an isolation transformer. The operating principles, the pulse-width modulation strategy and the control system for the proposed converter are presented. The proposed single-phase multilevel ac–dc–ac converter is composed mostly of low-power switches capable of generating input and output voltages with low harmonic content. The proposed configuration is compared with the conventional solution in terms of harmonic distortion, semiconductor losses and ratings of switches. Experimental results demonstrate the feasibility of the proposed configuration. The experimental verification of the proposed topology and control strategy was obtained by using IGBTs with dedicated drives and a digital signal processor TMS320F28335 with plug-in boards and sensors. 1 Introduction Single-phase ac–dc–ac converters are employed in a large number of applications, such as in uninterrupted power supplies [1, 2], active power filters [3, 4] and motor drive systems [5, 6]. Multilevel converters, compared with two-level converters, support half of the voltage stress on power switches for the same dc-link voltage and generate lower harmonics at the same switching frequency [7, 8]. One modular alternative to obtain multilevel converters is to build converters from the cascade of H-bridge converter [9-13]. The reduction of dc-link voltage fluctuations is another important issue for multilevel converters [14, 15]. It is also of interest to employ multilevel converters for low-power applications [16, 17]. Single-phase-to-single-phase conversion can be obtained by using the four-leg (full-bridge) topology [20]. Some works have proposed topologies with a reduced number of switches to supply single-phase loads [1, 18-20], two-phase loads [21] or three-phase loads [22-26]. A two-level three-leg converter (denoted in this paper as the conventional topology) [1, 18, 27], as shown in Fig. 1, is an interesting topology since it uses less switches than the four-leg topology and its performance is superior to the two-leg (half-bridge) topology [20]. Fig. 1Open in figure viewerPowerPoint Conventional configuration The conventional converter generates voltages vg and vl with three levels. Comparatively, the value of the current, voltage and power processed by each switch (qg, qh and ql) can be classified into high, low and medium, as shown in Table 1. Table 1. Switch stress – conventional configuration qg qh ql voltage high high high current high low high power high medium high From the conventional topology, this paper aims to investigate multilevel single-phase ac–dc–ac converter obtained by adding an H-bridge converter that: (a) generates voltages with more levels and (b) reduces the power processed by its switches. It is possible to consider three solutions to adding an H-bridge converter to the conventional topology in Fig. 1: (i) placing the H-bridge on the grid side (Fig. 2a), on the load side (Fig. 2b) or in the middle (i.e. a shared H-bridge) (Fig. 2c). The solution in Figs. 2a and b has some disadvantages, such as: H-bridge placed in regions of high current, difficulty of performing the dc-link voltages control, since those converters should operate without dc-link voltage source, and asymmetric grid (vg) and load (vl) converter voltages. The third configuration (Fig. 2c) is proposed and investigated in this paper. Fig. 2Open in figure viewerPowerPoint Converter topologies a H-bridge in the grid side b H-bridge in the load side c Shared H-bridge The proposed single-phase five-leg converter obtained from the connection of the three-leg converter (Converter A) with a shared H-bridge converter (Converter B) is shown in detail in Fig. 3a, whereas Fig. 3b presents its equivalent circuit. Fig. 3Open in figure viewerPowerPoint Proposed configuration a Converter topology b Equivalent circuit Table 2 shows the stress analysis of switches power for the proposed configuration. Table 2. Switch stress – proposed configuration qga qha, qhb1 and qhb2 qla voltage low low low current high low high power medium low medium Compared with the conventional converter (Fig. 1), the proposed converter (Fig. 3), allows the reduction of the voltage rating over all the power switches sharing a low-power H-bridge converter (Converter B) in the stage of low current (ih), consequently making the reduction of switching losses possible. Furthermore, additional voltage levels are created by generating voltage signals with lower harmonic content. Another important feature of this topology is that, although the sum of the dc-link capacitor voltages remains at the same amount of the conventional topology, the H-bridge converter operates without a power source in its dc-link. Consequently, the control of the dc-link voltages of the proposed topology is a very sensible issue, since all dc-links must operate in a balanced way. All these advantages offered by the proposed converter justify the increase to four switches compared with the conventional converter. This paper presents an overall control strategy, associated with the pulse-width modulation (PWM) command, for the proposed configuration that ensures the individual control of the capacitor dc-link voltages, a load voltage with a constant amplitude and frequency, sinusoidal current in the grid and maximisation of the grid power factor. Furthermore, the paper presents the analysis of the following parameters: harmonic distortion, current in the shared leg, dc-link capacitors stress and conduction and switching losses of the switches. The conventional converter is used as basis for performing the comparisons in order to evaluate gains and losses in the performance of the proposed configuration. 2 System model The following equations can be derived from the proposed converter (Fig. 3a) and its equivalent circuit (Fig. 3b) (1) (2) (3) (4)Equations (1) and (2) are derived from Kirchhoff's voltage law, whereas (3) and (4) are derived from Kirchhoff's current law. The input (vg) and output (vl) voltages of the converter can be written by applying Kirchhoff's voltage law in the circuit in Fig. 3b, as follows (5) (6)where , and . Additionally, in these equations , , , and are the pole voltages, zg = rg + plg, zf = rf + plf, with p = d / dt, and the symbols r and l represent the resistances and inductances of the inductors Lg and Lf. From the control point of view, grid and load controllers define vg to control ig and vl to control el, respectively. 3 PWM strategy The system control defines two reference voltages and to be generated by the converter. From and , it is required to calculate five pole voltages to command the converter. Therefore three auxiliary variables, denominated , and , must be introduced because only two voltages and are requested to the system control. The determination of the pole voltages of this converter can be made from the following steps: Step 1: Determine the voltages , and from the voltages , and auxiliary variable . The following relationships are found (7) (8) (9) The maximum and minimum limits for must be respected. These limits are (10) (11) (12)where the limits for the Converter A, and , can be obtained by and . The limits for the Converter B, and , are and . The voltages and are the references of the dc-link of the Converters A and B, respectively. In order to normalise the choice of the auxiliary variable and to satisfy its limits, parameter can be introduced, such that (13)After the selection of the value of , the auxiliary variable is calculated. Given , voltages , and are determined from (7) to (9). Section 5 will show that the values of the auxiliary variable change the converters power, and can be used to perform the dc-link voltage balance control. Step 2: Determine the reference pole voltages of Converter A. From , and the auxiliary variable , the reference pole voltages can be written as (14) (15) (16) The limit values of are given by and . The introduction of , allows for (17)After the selection of the value of , the auxiliary variable is calculated. Step 3: Determine the reference pole voltages of Converter B. From and the auxiliary variable , the reference pole voltages can be written as (18) (19) The limit values of are given by and . The introduction of , allows for (20)After the selection of the value of , the auxiliary variable is calculated. Considering μ equal to , note that when the maximum (μ = 1) or minimum (μ = 0) value is selected, one of the converters' legs operates with zero switching frequency. On the other hand, operation with the average value (μ = 0.5) generates pulse voltages centred inside the sampling period. Consequently, μ influences the harmonic distortion of the voltages generated by the converters and the switch loss, as shown in Section 6. Gating signals were obtained by comparing the reference pole voltages with one (1C), two (2C) and four (4C) high-frequency triangular carrier signals. The following settings of triangular carriers were used: one carrier (1C), two carriers spatially shifted by 90° (2C-90°), two carriers spatially shifted by 180° (2C-180°) and four carriers spatially shifted by 90° (4C-90°). 4 Current in the shared leg The current in the shared leg ih, present in the converters studied, is given by (21)Figs. 4a and b show the phasorial diagram of voltages and currents input and output of the converter. From (21), it can be seen that the lowest value of ih is found when the currents ig and if are in phase. This situation occurs when the angle between the input voltage and the output voltage of the converter (θgl) is equal to the power factor angle of the load (ϕl) as shown in Fig. 4b. Fig. 4Open in figure viewerPowerPoint Analysis of the current in the shared leg a Phasorial diagram for θgl ≠ ϕl b Phasorial diagram for θgl = ϕl c Amplitude of ih In Fig. 4c, the values of the amplitude of the current in the shared leg Ih in function of θgl are shown, with −90° ≤ θgl ≤ 90°. Curves of Ih for five power factor angles were obtained, where ϕl = {0, 10°, 20°, 30°, 40°}. The voltages vg and vl with 1 pu each were considered. The results shown in Fig. 4c confirm what had already been observed, that is, the minimum value of Ih at each curve is obtained in the case where θgl = ϕl. It is also observed that the larger the power factor angle is, the larger the value of Ih is for a given θgl. This conclusion is because of the fact that the reactive component of the output current increases as |ϕl| increases. Therefore the H-bridge converter (Converter B) was added in the stage of low current, reducing the switching losses. 5 Overall control strategy Fig. 5a presents the control block diagram of the proposed single-phase system. The average value of the dc-link capacitor voltage vCm = (vCa + vCb) / 2 is controlled by means of the controller RCm, of which the output is the amplitude of the reference current of grid system. The instantaneous reference current is obtained from a synchronisation with the grid voltage eg, performed by GEN-ig and phase-locked loop (PLL) blocks. The controller Rg defines the reference voltage . Fig. 5Open in figure viewerPowerPoint Overall control strategy a Control block diagram b Diagram of system implementation The variable is determined by the controller RCa in order to independently control the capacitor voltages vCa and vCb. The input of this controller is the dc-link capacitor voltage error . Depending on the direction of the current in the shared leg ih, or its complement, is selected to perform the PWM. If ih ≤ 0, the switch k is connected to point 1 selecting . If ih > 0, the switch k is connected to point 2 selecting . This way it is possible to direct more power to a converter over another. By varying , is varied, as indicated in (13). The auxiliary variable performs the division of the total voltage (and hence of the total power) input and output between the Converters A and B, as can be seen from (7) to (9). The dc-link capacitor voltage of the Converter A, vCa, can be controlled by . When is 0.5, the power supplied from each dc-link is equal. The PLL and GEN-el blocks (similar to Gen-ig) define the reference voltage and the controller Rl performs its control. The auxiliary variables are calculated from and the selected values for and . The PWM strategy defines the state of the switches (qga, qla, qha, qhb1 and qhb2) from the reference voltages. The diagram of system implementation is shown in Fig. 5b. The setup was built by employing ten insulated gate bipolar transistors (IGBTs), one vari-volt, six sensors and one digital signal processor (DSP). From the measured variables (eg, el, vCa, vCb, ig and ih), the DSP is used to obtain gating signals (qga, qha, qla, qhb1 and qhb2). 6 Comparison between conventional and proposed topologies The harmonic distortion, ratings of switches and semiconductor losses will be discussed next. 6.1 Harmonic distortion The harmonic distortion of the converter voltages was evaluated by using the weighted total harmonic distortion (THD) (WTHD), that is (22)where α1 is the amplitude of the fundamental voltage, αh is the amplitude of hth harmonic and Nh is the number of harmonics taken into consideration (Nh = 1000). The dc-links of the proposed topology were considered to be operating with equal voltages, that is, vCa = vCb = vC / 2, where vC is the value of the dc-link voltage of the conventional converter in Fig. 1. In Fig. 6, the WTHD of grid voltage vg generated by converters is shown, for the proposed configuration and for the conventional one, as a function of μ, where . The resultant voltage vg generated by the converter is responsible for controlling ig (see (1)), which means that this voltage is used to regulate the harmonic distortion of the grid current. Fig. 6Open in figure viewerPowerPoint WTHD comparison between the conventional and proposed topology as a function of μ The four used triangular carriers have a constant frequency equal to fsw = 10 kHz. This frequency corresponds to the switching frequency of the converter switches. It is noted that, with a single carrier (1C), the WTHDs of the input voltage vg have the same values both in the conventional topology and in the proposed topology for any value of μ. When two carriers PWM spatially shifted by 180° (2C-180°) are used in the proposed topology, only in μ = 0.5 the value of WTHD is equal to the value of WTHD of the conventional topology, for other values of μ the proposed topology has a smaller value of WTHD. Both with two carriers spatially shifted by 90° (2C-90°) and with four carriers spatially shifted by 90° (4C-90°), it is still possible to obtain lower values of WTHD, mainly in μ = 0.5, where the lowest value of WTHD is found for the proposed topology. Even for μ = 0 and 1, the configuration 4C-90°, unlike the configuration 2C-90°, has a low value of WTHD compared with the conventional topology. The explanation of the WTHD behaviour in Fig. 6 can be obtained from Fig. 7, which depicts the grid voltage of the conventional configuration and of the proposed configuration with 4C-90°, for μ = 0 and for μ = 0.5. Note that the number of levels generated by the proposed configuration is higher than that of the conventional configuration. In addition, the best result was obtained for the 4C-90° configuration with μ = 0.5. Table 3 presents the ig THD and vg WTHD values for the conventional converter and for the proposed converter (4C-90°) with μ = 0 and 0.5. Table 3. Harmonic distortion analysis WTHD, % THD, % conventional (μ = 0) 0.29 3.17 C-90° (μ = 0) 0.10 1.08 conventional (μ = 0.5) 0.15 1.70 C-90° (μ = 0.5) 0.05 0.62 Fig. 7Open in figure viewerPowerPoint Grid converter voltage a Conventional topology – μ = 0 b Conventional topology – μ = 0.5 c Proposed topology with 4C-90° – μ = 0 d Proposed topology with 4C-90° – μ = 0.5 6.2 Ratings of switches The voltage values of the dc-link are defined in order to meet the needs of input and output voltages (vg and vl) of converters in transient and steady states. For conventional and proposed topologies, the minimum value of the dc-link voltage (vC,min) required to generate a given pair of voltages vg and vl with 1 pu each is determined. The study was performed in function of the angle between the input voltage and the output voltage of the converter, θgl. In Fig. 8, the minimum value of the dc-link voltage obtained for the conventional and the proposed topologies with θgl ranging from −180° to 180° is shown. Fig. 8Open in figure viewerPowerPoint Dc-link voltage a Conventional topology b Proposed topology – converter A c Proposed topology – converter B d Proposed topology – total From Fig. 8a, assuming that voltages vg and vl equal to 1 pu must be generated by the converter, it is necessary to have a voltage 1 pu in the dc-link of the conventional topology, when |θgl| ≤ 60°. For |θgl| > 60°, the dc-link voltage increases as |θgl| increases, reaching 2 pu in |θgl| = 180°. To generate voltages vg and vl equal to 1 pu by the proposed topology, it is necessary to have a voltage of 0.5 pu in each dc-link, when |θgl| ≤ 29°. For |θgl| > 29°, the dc-link voltage of the Converter A increases as |θgl| increases, reaching 2 pu in |θgl| = 180°, whereas the dc-link voltage of the Converter B remains constant with value 0.5 pu. Therefore for |θgl| ≤ 29°, the proposed configuration requires half dc-link voltage in relation to the conventional one (0.5 pu). Consequently, the power and voltage ratings of each power switch in this converter is reduced. The current waveforms for the switches of the proposed topology are presented in Fig. 9. In this case, it can be noted that the root mean square (RMS) current values in the converter switches for a 1000 W RL load (cosφl = 0.90) are: , and . Therefore the current ratings of switches , qhb1 and qhb2 are approximately half the switches qga and qla. As seen in Section 4, the higher the value of load power factor, the lower the current in the shared leg ih. Fig. 9Open in figure viewerPowerPoint Current waveform for the switches a Switch qga b Switch qla c Switch qha d Switch qhb1 e Switch qhb2 6.3 Semiconductor losses The evaluation of the converter losses is obtained through the regression model presented in [28]. The switch loss model includes: (1) IGBT and diode conduction losses, (2) IGBT turn-ON losses, (3) IGBT turn-OFF losses and (4) diode turn-OFF energy. Table 4 shows conduction (Pcd), switching (Psw) and total (Pto) losses of the proposed topology and conventional topology obtained for switching frequency of fsw = 10 kHz and load with power equal to Pload = 1 kW. Table 4. Semiconductor losses analysis (10 kHz) Pcd, W Psw, W Pto, W conventional (μ = 0) 4.93 33.46 38.39 proposed (μ = 0) 6.67 19.86 26.53 conventional (μ = 0.5) 4.92 48.63 53.55 proposed (μ = 0.5) 6.67 31.79 38.46 As expected, the total losses for both topologies are smaller when μ = 0. This is because of the reduction of the switching losses, since some converter's legs operate in certain moments with a switching frequency equal to zero. Owing to the larger number of switches of the proposed topology, it is observed that the conduction losses are higher in this structure in relation to the conventional topology. On the other hand, the proposed configuration has the lowest switching losses, since the dc-link voltages that are imposed on their power switches are smaller than those of the conventional topology. Thus, from Table 4 it can be seen that the reduction in the switching losses are more significant in relation to the increase in conduction losses and thus the proposed topology has lower values of total losses when compared with conventional topology. When total losses are calculated for each leg, one obtains an idea of the power losses to which each switch will be submitted. In Table 5, a comparison is made between the total losses per leg of the proposed and conventional converters. Table 5. Total losses per leg μ = 0 μ = 0.5 conventional 12.80 17.85 proposed 5.31 7.69 The switching losses of the proposed topology can be further reduced since it is possible to reduce the switching frequency until the THD of this converter becomes equal to that of the conventional converter, as shown in Table 6. In this case, the switching frequency was reduced from 10 to 3.5 kHz. Table 6. Semiconductor losses analysis – reduced switching frequency (3.5 kHz) Pcd, W Psw, W Pto, W proposed (μ = 0) 6.94 7.00 13.94 proposed (μ = 0.5) 6.96 11.52 18.48 7 Comparison between the proposed topology and two other ac–dc–ac converter alternatives In this section, comparisons of the proposed topology to two other ac–dc–ac converter alternatives from literature are performed in terms of number of components, semiconductor losses and harmonic distortion. In [29], a three-level three-leg ac–dc–ac converter with neutral-point diode-clamped (NPC) for single-phase applications is investigated. This topology is composed of 1 dc-link, 12 switches and 6 diodes. Compared with the proposed topology, the NPC converter presents two additional switches and six extra diodes. While the proposed topology has only four switches at the stage of high current, the NPC converter has eight. A single-phase ac–dc–ac with a cascaded connection of two three-arm converters (2 × 3-arm) is presented in [30]. This converter is composed of 2 dc-links and 12 switches. Compared with the proposed topology, the 2 × 3-arm converter presents two additional switches. Furthermore, it presents eight switches at the stage of high current. Considering the operations with same THD for all the topologies, Table 7 shows conduction , switching and total losses for the converter alternatives (NPC [29] and 2 × 3-arm [30]) normalised by the losses of the proposed converter. The analysis was performed considering μ = 0, but all conclusions are valid for μ = 0.5. As expected, the total losses of the proposed converter are lower than those of the converters NPC and 2 × 3-arm. Table 7. Comparison between converters – semiconductor losses analysis NPC 1.36 1.51 1.47 x3-arm 1.44 1.31 1.34 The NPC converter generates input and output voltages with five levels. However, the 2 × 3-arm converter and the proposed topology can generate voltages with up to nine levels when operating with different dc-link voltage values (see the next section). In this situation, the additional voltage levels which were created generate voltage signals with lower harmonic content. 8 Proposed topology operating with different dc-link voltage values In this section, the situation in which the proposed topology operates with different dc-link voltage values is analysed. In order to obtain nine voltage levels, the dc-links voltage of the Converters A and B must be equal to vCa = vC / 4 and vCb = 3vC / 4, respectively. Fig. 10 shows the grid voltages vg generated by the converter. Fig. 10a is obtained by keeping the switching frequency constant, so that the switching between two levels is carried out by changing the state of only one power switch. By increasing the switching frequency between levels (vC / 4 and vC / 2) and (−vC / 4 and −vC / 2), it is possible to generate grid voltage in which the voltage switches between only the two nearest levels (Fig. 10b). Fig. 10Open in figure viewerPowerPoint Grid converter voltage a Case 1 b Case 2 In both cases, it is possible to obtain a harmonic distortion close to the best one obtained with equal dc-link voltage, see Table 3 for 4C-90° (μ = 0.5), but with smaller average switching frequency. Consequently, the switching and total losses obtained, shown in Table 8, are smaller than those obtained with equal dc-link voltage (see Table 4). Table 8. Semiconductor losses – operation with different dc-link voltage values Pcd, W Psw, W Pto, W case 1 6.62 12.57 19.19 case 2 6.58 11.47 18.05 9 Generalisation of the proposed topology The proposed configuration can be generalised in order to increase the number of levels by introducing other H-bridge converters. Fig. 11 shows the generalised system with N H-bridge converters connected in series. From the proposed topology previously presented, the following equations can be derived (23) (24)where (25) Fig. 11Open in figure viewerPowerPoint Generalisation of the proposed topology In addition, the index j may range from b to N. Based on the previous discussion, the overall control of the system can be derived, including the PWM strategy. 10 Simulation results The simulation results were obtained for the proposed converter operating with a dc-link capacitor equal to C = 2200 μF, dc-link voltages equal to 65 V, switching frequency equal to 10 kHz and RL load (El = 100 V and cos ϕl = 0.90). A variation in load was performed at t = 1 s to evaluate the performance of the proposed control system, as shown in Fig. 12. The transient load was made by keeping the power factor constant and decreasing the impedance amplitude of 40% in relation to the initial value. After the transient state, the dc-link capacitor voltages are balanced again, the grid current increases and the load voltage remains constant. Fig. 12Open in figure viewerPowerPoint Simulation results – effect of load variation on the system a dc-link capacitor voltages (vCa and vCb) b Grid current (ig) c Filtered load voltage (el) 11 Experimental results The proposed configuration shown in Fig. 3a was implemented in a laboratory. The setup was built by employing IGBTs with dedicated drives (SKHI23). A DSP TMS320F28335 with plug-in boards and sensors was used to generate the gating signals and to measure variables. The experimental development platform operated with the following parameters: dc-link capacitor equal to C = 2200 μF, dc-link voltages equal to 65 V, switching frequency equal to 10 kHz and RL load (El = 100 V, cos ϕl = 0.98, 600 W). Experimental results of the proposed topology for 2C-90° with μ = 0.5 are presented in Fig. 13. This oscillogram figure shows the controlled variables obtained in steady state: the grid current (ig), the load voltage (el) and the dc-link capacitor voltages (vCa and vCb). It can be seen that all variables are adequately controlled. Fig. 13Open in figure viewerPowerPoint Experimental results of the proposed topology for 2C-90° with μ = 0.5 Other details of the system operation can be seen from Fig. 14 (points obtained from the oscillogram). Figs. 14a and b show the variables at the final time interval of the dc-link voltage shown in Fig. 14c. The grid power factor control is shown in Fig. 14a, where one can observe the synchronism between the grid voltage and the grid current. Fig. 14b shows the grid converter voltage (vg). The dc-link voltages shown in Fig. 14c are obtained with the balance control (see Fig. 5) disconnected during the interval 0 ≤ t ≤ 2.7 s and connected during the interval 2.7 s < t ≤ 5 s. It can be seen that when the balance control is not active, the dc-link capacitor voltages are unbalanced. Fig. 14Open in figure viewerPowerPoint Experimental results a Grid voltage (eg) and current (ig) b Grid converter voltage (vg) c dc-link capacitor voltages (vCa and vCb) 12 Conclusions A ac–dc–ac multilevel converter for single-phase applications has been proposed in this paper. From this converter, a generalised converter topology has also been proposed. The system model, the overall control system and the PWM strategy have been presented. It has been shown that the proposed PWM strategy permits the balancing of the dc-link voltages. A comparison between the proposed and conventional configurations has been carried out in this paper. Compared with the conventional topology, the proposed system permits reducing the voltages and the power processed by the converter switches. Furthermore, the proposed converter improves the THD of the current. In addition, the total losses of the proposed converter may be lower than that of the conventional counterpart. Experimental results validate the theoretical considerations. The aforementioned benefits justify the proposed system, because of the increase of the number of switches. 13 Acknowledgment The authors acknowledge the financial support of the National Council of Technological and Scientific Development (CNPq/Brazil). 14 References 1Choi J.-H., Kwon J.-M.B., Jung J.-H., and Kwon B.-H.: 'High-performance online UPS using three-leg-type converter', IEEE Trans. Ind. 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