A twin-well CMOS process employing high-energy ion implantation
1986; Institute of Electrical and Electronics Engineers; Volume: 33; Issue: 4 Linguagem: Inglês
10.1109/t-ed.1986.22511
ISSN1557-9646
Autores Tópico(s)Advancements in Semiconductor Devices and Circuit Design
ResumoA twin-well CMOS process has been developed using ion implantation with energies up to 1 MeV. The high-energy ion-implantation steps eliminate the need for extended processing times at high temperatures. As a consequence, this permits an increase in packing density, independent control of critical electrical parameters, and simplified processing. The resulting process includes advantages of recent developments in bulk CMOS: an n-type isolation well in a p-p + substrate and retrograde wells. This paper discusses the processing steps involved and provides the resulting device characteristics. An interesting application of the process is also presented, which is the realization of a gate array with TTL-compatible input and output buffers.
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