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Horus: Large-Scale Symmetric Multiprocessing for Opteron Systems

2005; Institute of Electrical and Electronics Engineers; Volume: 25; Issue: 2 Linguagem: Inglês

10.1109/mm.2005.28

1937-4143

R. Kota, Richard Oehler,

Distributed and Parallel Computing Systems

Horus lets server vendors design up to 32-way Opteron systems. Horus is the only chip that targets the Opteron in an SMP implementation. By implementing a local directory structure to filter unnecessary probes and by offering 64 Mbytes of remote data cache, the chip significantly reduces overall system traffic as well as the latency for a coherent hypertransport transaction.