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Control of surface charging during high current ion implantation

1989; Elsevier BV; Volume: 37-38; Linguagem: Inglês

10.1016/0168-583x(89)90245-0

1872-9584

Michael Current, Anirban Bhattacharyya, M. Khid,

Semiconductor materials and interfaces

Control of wafer surface charge buildup during high current implantation is a leading concern for yield and reliability of thin dielectric layers in CMOS devices. Some key parameters in ion implantation system design are wafer scan speed, ion beam current density and the use of low energy electrons to "clamp" surface potentials to levels below the onset of damage. Results of measurements of oxide yield highlight the importance of the amount of charge delivered per pass of a wafer through the ion beam. Catastrophic failure was observed as the charge per pass was increased towards 3.3 × 10−6 C/cm2. Experimental results for Qpp f As and B beams in the Precision Implant 9000 are also presented.