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Degradation of polycrystalline HfO 2 -based gate dielectrics under nanoscale electrical stress

2011; American Institute of Physics; Volume: 99; Issue: 10 Linguagem: Inglês

10.1063/1.3637633

1520-8842

V. Iglesias, Mario Lanza, K. Zhang, A. Bayerl, M. Porti, M. Nafrı́a, X. Aymerich, Günther Benstetter, Zebang Shen, G. Bersuker,

Advanced Memory and Neural Computing

The evolution of the electrical properties of HfO2/SiO2/Si dielectric stacks under electrical stress has been investigated using atomic force microscope-based techniques. The current through the grain boundaries (GBs), which is found to be higher than thorough the grains, is correlated to a higher density of positively charged defects at the GBs. Electrical stress produces different degradation kinetics in the grains and GBs, with a much shorter time to breakdown in the latter, indicating that GBs facilitate dielectric breakdown in high-k gate stacks.