Optimized thermal processing for Ti-capped CoSi2 for 0.13 μm technology
2001; Elsevier BV; Volume: 55; Issue: 1-4 Linguagem: Inglês
10.1016/s0167-9317(00)00442-1
ISSN1873-5568
AutoresRichard Lindsay, A. Lauwers, M. de Potter, N. Roelandts, C. Vrancken, Karen Maex,
Tópico(s)Force Microscopy Techniques and Applications
ResumoCoSi2 formed using a Ti cap has been shown to reduce any oxide or contaminants present during silicide growth to improve the uniformity of the silicide. However, as transistor dimensions shrink, a concern in using CoSi2 is the thermal process window for the second RTP step (RTP2). Thinner silicides agglomerate at lower temperatures but a minimum temperature is required for a uniform silicide with low junction leakage. This paper describes the results of a detailed investigation into the thermal processing of thin Ti-capped CoSi2 compatible with 0.13 μm CMOS technology. Ti-capped CoSi2 films of varying thickness on both poly and active regions were studied for three junction dopants, As, BF2, and B. The parameters investigated in the thermal processing were the temperature, time and ramp rates for RTP2. Sheet resistance, diode leakage, and interface roughness were measured as a function of the thermal processing. The results show that the optimal RTP2 thermal budget for thin Ti-cap CoSi2 on devices is 800°C for 120 s with high ramp rates giving possible leakage improvement.
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