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A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

2014; Institute of Electrical and Electronics Engineers; Volume: 50; Issue: 1 Linguagem: Inglês

10.1109/jssc.2014.2347353

1558-173X

Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori,

Interconnection Networks and Systems

This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The key design highlights are as follows. 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2 GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28 nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg), resulting in 24% leakage reduction of L1 cache. 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 20% dynamic power reduction, 29% leakage power reduction and 40 mV improvement of minimum operation voltage are achieved. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC voltage drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.