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Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application

2013; ACM SIGARCH; Volume: 41; Issue: 5 Linguagem: Inglês

10.1145/2641361.2641374

1943-5851

Takeshi Ohkawa, Uetake Daichi, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba,

Modular Robots and Swarm Intelligence

A platform for networked FPGA system design, which is named "ORB Engine", is proposed to add more controllability and design productivity on FPGA-based systems composed of software and hardwired IPs. A developer can define an object-oriented interface for the circuit IP in FPGA, and implement the control sequence part using Java. The circuit IP in FPGA can be handled through object-oriented interface from variety of programing languages like C++, Java, Python, Ruby and so on. Application specific and high-efficiency circuit for ORB (Object Request Broker) protocol processing is synthesized from easy-handling Java code using JavaRock Java-to-HDL synthesizer within the de-facto standard CORBA (Common Object Request Broker Architecture). The measurement result shows a very low latency as low as 200us of UDP/IP packet in/out and exhibits a fluctuation free delay performance, which is desirable for real-time applications.