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Thermal stresses in 3D IC inter-wafer interconnects

2005; Elsevier BV; Volume: 82; Issue: 3-4 Linguagem: Inglês

10.1016/j.mee.2005.07.053

1873-5568

Jing Zhang, Max O. Bloomfield, Jian‐Qiang Lu, R.J. Gutmann, Timothy S. Cale,

Copper Interconnects and Reliability

We present a finite element based analysis to determine if thermally induced stresses in inter-wafer Cu via structures in 3D ICs using BCB-bonded wafers is a potential reliability problem. Experimental information on thermal stresses or stress-induced failures of 3D ICs is not available in the literature. Therefore we first partially validate our approach by comparing computed results against experimental data on via test structures from planar ICs. Computed von Mises stresses show that the predicted failure agrees with the results of thermal cycle experiments when SiLK is used as a dielectric [R.G. Filippi, J.F. McGrath, T.M. Shaw, et al. Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric, in: 2004 IEEE International Reliability Physics Symposium. Proceedings, 25–29 April, 2004. IEEE, Phoenix, AZ, USA, p. 61–67]. Simulations show that no yielding is expected in vias embedded in SiCOH, which is also in agreement with experiment [D. Edelstein, H. Rathore, C. Davis, et al. Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL, in 2004 IEEE International Reliability Physics Symposium. Proceedings, 25–29 April, 2004, IEEE, Phoenix, AZ, USA, p. 316–319]. The approach is then employed to study thermal stresses in inter-wafer Cu vias in 3D IC structures bonded with BCB using a process developed at the Focus Center–New York. We conclude that there is a concern regarding the stability of inter-wafer Cu vias. Target values for design parameters, e.g., inter-wafer via size, pitch, and the thickness of BCB, are estimated. Simulations show that the von Mises stresses in inter-wafer Cu vias decrease with decreasing pitch length at constant via size, increase with decreasing via size at constant pitch, and decrease with decreasing BCB thickness. For 1 μm via diameter and 5 μm pitch, computations indicate that the thickness of BCB should be less than 1 μm to avoid plastic yield of Cu vias.