Produção Nacional
Signal Integrity Enhancement in Digital Circuits
2008; Institute of Electrical and Electronics Engineers; Volume: 25; Issue: 5 Linguagem: Inglês
10.1109/mdt.2008.146
ISSN1558-1918
AutoresJorge Filipe L.C. Semio, Marcial Jesus Rodriguez Irago, Juan J. Rodríguez-Andina, Leonardo Bisch Piccoli, F. Vargas, Marcelino Santos, I.C. Teixeira, J.P. Teixeira,
Tópico(s)Advancements in PLL and VCO Technologies
ResumoThis article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to power line fluctuations while maintaining the at-speed clock rate.
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