PADI, an Ultrafast Preamplifier - Discriminator ASIC for Time-of-Flight Measurements
2014; Institute of Electrical and Electronics Engineers; Volume: 61; Issue: 2 Linguagem: Inglês
10.1109/tns.2014.2305999
ISSN1558-1578
AutoresM. Ciobanu, N. Herrmann, K. D. Hildenbrand, M. Kiš, A. Schüttauf, H. Flemming, H. Deppe, S. Löchner, J. Frühauf, I. M. Deppner, P.-A. Loizeau, M. Träger,
Tópico(s)Integrated Circuits and Semiconductor Failure Analysis
ResumoThe design of a general-purpose PreAmplifier-DIscriminator ASIC chip, PADI, is presented in this article. PADI is intended to be used as Front-End-Electronics (FEE) for reading out the timing Resistive-Plate Chambers (RPCs) in the time-of-flight (ToF) wall of the CBM detector for the future FAIR facility in Darmstadt-Germany, which will comprise about 100,000 channels in a 150 m 2 area. The evolution of this 0.18 μm CMOS technology design will be presented, from the first prototype PADI-1 to the last one, PADI-8, as well as its features and test results.
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