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A reconfigurable neuroprocessor for self-organizing feature maps

2013; Elsevier BV; Volume: 112; Linguagem: Inglês

10.1016/j.neucom.2012.11.045

1872-8286

Jan Lachmair, Erzsébet Merényi, Mario Porrmann, Ulrich Rückert,

CCD and CMOS Imaging Sensors

In this paper we compare a scalable FPGA-based hardware accelerator for the emulation of Self-Organizing Feature Maps (SOMs) with a multi-threaded software implementation on a state-of-the-art multi-core microprocessor. After discussing the mapping of SOMs to the reconfigurable digital hardware implementation, we present how the modular system architecture can be flexibly adapted to various application datasets as well as to variants of SOMs like Conscience SOM. Hyperspectral image processing is used as a benchmark scenario for the comparison of our FPGA-based hardware accelerator and state-of-the-art multi-core microprocessors. The hardware costs, power consumption, and scalability of the FPGA-based accelerator using Xilinx Virtex-4 FPGAs are discussed. For the real-world datasets used here, which require large SOMs, a speedup and energy reduction of one order of magnitude are achieved.