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A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

2005; Institute of Electrical and Electronics Engineers; Volume: 40; Issue: 11 Linguagem: Inglês

10.1109/jssc.2005.857360

1558-173X

Hyung-Rok Lee, Moon-Sang Hwang, Bong-Joon Lee, Youngdeok Kim, Do-Hwan Oh, Jaeha Kim, Sanghyun Lee, Deog‐Kyoon Jeong, W. Kim,

Analog and Mixed-Signal Circuit Design

This paper describes the design and the implementation of a fully integrated 10 Gb Ethernet transceiver in a 0.13-/spl mu/m CMOS process using only a 1.2 V supply. A coarse control algorithm that combines a voltage range monitoring circuit with a frequency lock detector provides a robust operation against process, voltage, and temperature (PVT) variations for a VCO with a ring oscillator. With the use of a blind oversampling DPLL architecture, four channels of XAUI transceivers can share a single PLL, eliminating the clock synchronization problem between channels. Also, the total number of clock domains for the entire chip is reduced to three, making the integration of the XAUI with the 10G transceiver much simpler. The test chip consumes 898 mW from a 1.2 V supply.