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ATLAS I: a single-chip, gigabit ATM switch with HIC/HS links arid multi-lane back-pressure

1998; Elsevier BV; Volume: 21; Issue: 7-8 Linguagem: Inglês

10.1016/s0141-9331(98)00041-6

1872-9436

Manolis Katevenis, Dimitrios Serpanos, Georgios Dimitriadis,

Parallel Computing and Optimization Techniques

ATLAS I is a single-chip ATM switch that uses IEEE Std. 1355 ‘HIC’ gigabit links arid implements optional credit-based flow control. It is a 16 × 16 switch with 20 Gb s−1 aggregate I/O throughput, three priority levels, 256-cell shared buffer, arid 54 output queues achieving submicrosecond cut-through latency; furthermore, it supports rate-based flow control, link bundling, multicasting, arid load monitoring. ATLAS I is targeted at use in interconnections ranging from wide area (WAN) to LAN arid desktop (DAN) networking, arid supports a mixture of services from real-time, guaranteed quality-of-service to best-effort, bursty amd flooding traffic. Target applications range from telecom to multimedia arid multiprocessor NOWs. ATLAS I implements a multi-lane back-pressure (credit) flow control scheme, which in conjunction with shared buffering provides high performance arid robust operation, since it eliminates the head-of-line blocking problems of input queuing arid single-lane back-pressure. We present the queue model of the switch, we describe how multi-lane back-pressure is added on top of single-lane 1355 standard links, as an optional extension, arid we show how the link interfaces are implemented arid how their parameters are evaluated.