Artigo Acesso aberto Revisado por pares

Design of Encoder and Decoder for LDPC Codes Using Hybrid H-Matrix

2005; Electronics and Telecommunications Research Institute; Volume: 27; Issue: 5 Linguagem: Inglês

10.4218/etrij.05.0905.0015

ISSN

2233-7326

Autores

Chanho Lee,

Tópico(s)

Cooperative Communication and Network Coding

Resumo

ETRI JournalVolume 27, Issue 5 p. 557-562 ArticleFree Access Design of Encoder and Decoder for LDPC Codes Using Hybrid H-Matrix Chanho Lee, Chanho LeeSearch for more papers by this author Chanho Lee, Chanho LeeSearch for more papers by this author First published: 01 October 2005 https://doi.org/10.4218/etrij.05.0905.0015Citations: 8 Chanho Lee (phone: + 82 2 820 0710, email: [email protected]) is with the School of Electronic Engineering, Soongsil University, Seoul, Korea. AboutPDF ToolsExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinkedInRedditWechat Abstract Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a 0.35 µm CMOS standard cell library. References 1F.E. O'Brien and R.D. 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