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Realization of 850V breakdown voltage LDMOS on Simbond SOI

2011; Elsevier BV; Volume: 91; Linguagem: Inglês

10.1016/j.mee.2011.10.014

1873-5568

Zhongjian Wang, Xinhong Cheng, Dawei He, Chao Xia, Dawei Xu, Yuehui Yu, Dong Zhang, Yanying Wang, Yuqiang Lv, Dawei Gong, Shao Kai,

Advancements in Semiconductor Devices and Circuit Design

In this paper, 850 V breakdown voltage LDMOS fabricated on Simbond SOI wafer are reported. Simbond SOI wafers with 1.5 μm top silicon, 3 μm buried oxide layer, and n-type heavy doped handle wafers are used. In order to achieve uniform lateral electric field and shorten the vertical impact ionization integration path simultaneously, an optimized 60 μm drift region implant mask is designed to realize a linearly graded doping profile, and silicon thickness in the drift region is reduced from 1.5 μm to about 0.26 μm by thick field oxide process. CMOS compatible SOI LDMOS processes are designed and implemented successfully. Off-state breakdown voltage of SOI LDMOS can reach 850 V, and the specific on-resistance is 56 Ω mm2. Experimental results also show the thickness of the top silicon in the drift region has a good uniformity. The performance of SOI LDMOS indicated that Simbond SOI wafers are good choice for thin film high voltage devices.