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An FPGA-based In-Line Accelerator for Memcached

2013; Institute of Electrical and Electronics Engineers; Volume: 13; Issue: 2 Linguagem: Inglês

10.1109/l-ca.2013.17

2473-2575

Maysam Lavasani, Hari Angepat, Derek Chiou,

Embedded Systems Design Techniques

We present a method for accelerating server applications using a hybrid CPU+FPGA architecture and demonstrate its advantages by accelerating Memcached, a distributed key-value system. The accelerator, implemented on the FPGA fabric, processes request packets directly from the network, avoiding the CPU in most cases. The accelerator is created by profiling the application to determine the most commonly executed trace of basic blocks which are then extracted. Traces are executed speculatively within the FPGA. If the control flow exits the trace prematurely, the side effects of the computation are rolled back and the request packet is passed to the CPU. When compared to the best reported software numbers, the Memcached accelerator is 9.15× more energy efficient for common case requests.