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A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE

2002; Institute of Electrical and Electronics Engineers; Volume: 37; Issue: 1 Linguagem: Inglês

10.1109/4.974540

1558-173X

O. Oliaei, P. Clement, P. Gorisse,

Radio Frequency Integrated Circuit Design

A sigma-delta modulator designed as part of a complete GSM/EDGE (enhanced data rate for GSM evolution) transceiver is described. High-resolution wide-band analog-to-digital converters enable the receiver to rely on digital processing, rather than analog filtering, to extract the desired signal from blocking channels. High linearity and low power consumption are the most stringent requirements for the converters in this wireless application. A single-bit 2-2-cascaded modulator operating at 13 MHz has been adopted for high linearity and stability. Low-power low-voltage techniques have been applied along with a top-down design approach in order to minimize the power dissipation. The /spl Sigma//spl Delta/ modulator achieves 13.5 bits of resolution over a bandwidth of 180 kHz while dissipating 5 mW from 1.8-V and 2.4-V supplies. The circuit has been implemented in the CMOS portion of a 0.4-/spl mu/m (drawn) BiCMOS technology and occupies an active area of 0.4 mm/sup 2/.