Artigo
Ultra-linear pulser for testing fast integrating ADCs
1980; Elsevier BV; Volume: 173; Issue: 3 Linguagem: Inglês
10.1016/0029-554x(80)90920-9
ISSN1878-3759
Autores Tópico(s)VLSI and Analog Circuit Testing
ResumoA simple pulser employing a VMOS FET has been built and tested. Over the range of injected charge from 15 to 500 pC, the pulser is found to be linear to better than 0.04%.
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