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A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

2005; Institute of Electrical and Electronics Engineers; Volume: 40; Issue: 1 Linguagem: Inglês

10.1109/jssc.2004.837983

1558-173X

Sang-Bo Lee, Seong-Jin Jang, Jin-Seok Kwak, Sang-Jun Hwang, Seong‐Ho Cho, Min Sang Park, Ho-Kyoung Lee, Woojin Lee, Yu-Rim Lee, Young-Cheol Cho, Hyoung-Jo Heo, Won-Hwa Shin, Jong‐Soo Lee, Yun-Sik Park, Seok Jung Kim, Young-Uk Jang, Seok-Won Hwang, Young-Hyun Jun, Soo-In Cho,

Low-power high-performance VLSI design

An 8 M /spl times/ 32 GDDR (graphic DDR) SDRAM operating up to 800-MHz clock (CLK) frequency is described. The GDDR SDRAM demands an effective control of CAS latency due to the large and wide number of CAS latencies at the CLK frequency. A wave-pipelined CAS latency control circuit is proposed to provide stable operation for the large and wide number of CAS latencies. The increase of CAS latency also causes a degradation of data bus efficiency at high-speed operation due to the large gap between input data (DINs) and output data (DOUTs) at the operation of write followed by read. A gapless write to read scheme improves the data bus efficiency by separating write data-path from read data-path for different banks accesses. Partial array activation commands can reduce the peak current, preventing the reduction of the data retention time of DRAM cells at high-speed operation. The GDDR SDRAM operates successfully at the CLK frequency of 800 MHz at 2.1 V and 700 MHz at 1.8 V, respectively. The power consumption is measured to be /spl sim/2 W at 1.9 V.