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Physical limits for scaling of integrated circuits

2010; IOP Publishing; Volume: 248; Linguagem: Inglês

10.1088/1742-6596/248/1/012059

1742-6596

Waldemar Nawrocki,

Integrated Circuits and Semiconductor Failure Analysis

In this paper we discuss some physical limits for scaling of devices and conducting paths inside of semiconductor integrated circuits (ICs). Since 40 years only a semiconductor technology, mostly the CMOS and the TTL technologies, are used for fabrication of integrated circuits in the industrial scale. Miniaturization of electronic devices in integrated circuits has technological limits and physical limits as well. In 2010 best parameters of commercial ICs shown the dual-core Intel Core i5-670 processor manufactured in the technology of 32 nm. Its clock frequency in turbo mode is 3.73 GHz. A forecast of the development of the semiconductor industry (ITRS 2009) predicts that sizes of electronic devices in ICs circuits will be smaller than 10 nm in the next 10 years. The physical gate length in a MOSFET will even amount 7 nm in the year 2024. At least 5 physical effects should be taken into account if we discuss limits of scaling of integrated circuits.