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A sub-picojoule-per-bit CMOS photonic receiver for densely integrated systems

2009; Optica Publishing Group; Volume: 18; Issue: 1 Linguagem: Inglês

10.1364/oe.18.000204

1094-4087

Xuezhe Zheng, Frankie Liu, Dinesh Patil, Hiren Thacker, Ying Luo, Thierry Pinguet, Attila Mekis, Jin Yao, Guoliang Li, Jing Shi, Kannan Raj, Jon Lexau, Elad Alon, Ron Ho, J. E. Cunningham, Ashok V. Krishnamoorthy,

Optical Network Technologies

We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible.