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Two gates are better than one [double-gate MOSFET process]

2003; Institute of Electrical and Electronics Engineers; Volume: 19; Issue: 1 Linguagem: Inglês

10.1109/mcd.2003.1175108

8755-3996

P. M. Solomon, K.W. Guarini, Yifan Zhang, K. Chan, E.C. Jones, G. M. Cohen, Azalia A. Krasnoperova, Maria Ronay, O. Dokumaci, H.J. Hovel, J. J. Bucchignano, C. Cabral, C. Lavoie, V. Ku, D. Boyd, K. Petrarca, Jung Ho Yoon, I. Babich, J Treichler, P. Kozlowski, J. Newbury, C. D’Emic, R.M. Sicina, J. Benedict, H.‐S. Philip Wong,

Integrated Circuits and Semiconductor Failure Analysis

A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.