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An ECL 5000-gate gate array with 190-ps gate delay

1986; Institute of Electrical and Electronics Engineers; Volume: 21; Issue: 2 Linguagem: Inglês

10.1109/jssc.1986.1052509

1558-173X

M. Tatsuki, Shigeaki Kato, M. Okabe, Hideki Yakushiji, Y. Kuramitsu,

Advancements in Semiconductor Devices and Circuit Design

The authors describe an ECL 5000-gate gate array for use in mainframe computers. A modified paired-gate cell is introduced to obtain a high utilization of elements and a high functionality. The appropriate selection of emitter-follower currents is performed to achieve high performance for the LSI. The basic gate delay time is 190 ps/gate at a power dissipation of 2.56 mW/gate by using advanced bipolar transistors. To examine the performance of this gate array, a 16-bit multiplier has been implemented by utilizing the automatic CAD system and mounted on a 148-pin pin-grid array package. The multiplication time is 8.3 ns.