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A 20-V four-quadrant CMOS analog multiplier

1985; Institute of Electrical and Electronics Engineers; Volume: 20; Issue: 6 Linguagem: Inglês

10.1109/jssc.1985.1052454

1558-173X

J.N. Babanezhad, Gábor C. Temes,

Low-power high-performance VLSI design

A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilbert's six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the MOS GSTC. The voltage ranges are further increased by introducing the folded CMOS GSTC.